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| sajattack[m] | seems #siglenthax died with freenode | 05:37 |
|---|---|---|
| sajattack[m] | unless there's a libera with another name | 05:37 |
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| _florent_ | sajattack[m]: Hi, for things related to https://github.com/360nosc0pe/scope you can discuss it here | 07:31 |
| sajattack[m] | Alright thanks | 07:32 |
| _florent_ | for now the project is pause, but I'm playing to play with it again with micropython | 07:32 |
| sajattack[m] | I ordered an SDS1104X-E yesterday and was trying to decipher the eevblog instructions but I think I've figured it out now | 07:33 |
| sajattack[m] | I was curious if your yocto would work with default gateware or only the custom bitstream? | 07:33 |
| _florent_ | with micropython configuring/handling the peripherals, providing a standalone scope and processing still done on the Host with GlScopeClient | 07:33 |
| sajattack[m] | redbeard in the unnamed re discord has made some progress towards a buildroot/yocto for the default gateware as I understand it | 07:35 |
| _florent_ | sajattack[m]: I sorry I haven't used the yocto part, on my side I reused the existing reverse engineering of the Scope and have been porting LiteX to it | 07:35 |
| _florent_ | so only focused on the PL side | 07:35 |
| sajattack[m] | Oh I didn't realize it was someone else | 07:36 |
| _florent_ | @ | 07:37 |
| _florent_ | G33KatWork here has been involved in the yocto part IIRC | 07:37 |
| _florent_ | If you want to play with the default gateware/software over SCPI, there are also some efforts to support it with GLScopeClient (#scopehal) | 07:41 |
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| tnt | Any special trick to get litex to generate a .bin instead of .bit ? | 09:08 |
| _florent_ | tnt: With a XIlinx device, you can use this for QSPI: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/sqrl_acorn.py#L124-L131 | 09:37 |
| tnt | Heh, build <> target env. | 09:38 |
| sajattack[m] | I think the relevant bit is line 130 | 09:44 |
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| sajattack[m] | Or maybe I misunderstood your comment | 09:46 |
| tnt | Oh no, it's me ... I confused channels. | 09:48 |
| tnt | I also asked somewhere else where to program the fpga with OSS tools and I thought this was an answer to that. | 09:48 |
| tnt | I ended up instaling Vivado Lab edition to the remote machine so I could program the fpga. | 10:02 |
| tnt | Unfortunately ... bitstream doesn't seem to do anything :/ | 10:03 |
| tnt | If I just have the SoCCore and pretty much nothing else, I should still see something on the serial right ? | 10:04 |
| sajattack[m] | I think so | 10:07 |
| tnt | Damn, being remote suck ... can't check wiring, can't see if leds are blinking, ... | 10:08 |
| _florent_ | tnt: OpenOCD will work allow to load the .bit, but not sure anyone did the BSCAN<>SPI proxy bitstreams for Ultrascale | 10:39 |
| _florent_ | tnt: you can try a very minimal bistream: | 10:42 |
| _florent_ | with LiteX, set with_uart to False | 10:42 |
| _florent_ | and | 10:42 |
| _florent_ | serial_pads = platform.request("serial") | 10:42 |
| _florent_ | self.comb += serial_pads.tx.eq(serial_pads.rx) | 10:42 |
| _florent_ | Then just see if you get an echo :) | 10:43 |
| tnt | _florent_: Ah thanks, I was just looking how to do that :p ( do an echo without conflicting ). | 10:52 |
| tnt | Well, echo seems to work. | 11:05 |
| _florent_ | ok, so UART is ok, maybe an issue with the clock? | 11:13 |
| _florent_ | you can test something like this: | 11:13 |
| _florent_ | https://hastebin.com/olomacubit.pl | 11:13 |
| tpb | Title: hastebin (at hastebin.com) | 11:13 |
| _florent_ | ah, you can directly pass serial_pads to IOStreamer | 11:14 |
| _florent_ | otherwise can you share the target file you were testing? | 11:15 |
| tnt | Sure I can upload them, gimme a sec. | 11:16 |
| tnt | _florent_: https://people.osmocom.org/~tnt/stuff/adi/ | 11:18 |
| tpb | Title: Index of /~tnt/stuff/adi/ (at people.osmocom.org) | 11:18 |
| _florent_ | it looks fine, are you sure the 122.88MHz clock is enabled at startup? | 11:21 |
| tnt | I am not ... I just hope so because it's the only clock source to the PL I could find on this board ... | 11:23 |
| _florent_ | If the PCIe is plugged, you can probably get the 100MHz PCIe clock with something like this: | 11:29 |
| _florent_ | https://www.irccloud.com/pastebin/Nzx47rR5/ | 11:29 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 11:29 |
| tnt | _florent_: I'll give that a shot. | 11:31 |
| tnt | ERROR: [DRC REQP-1929] IBUFDS_GTE4_O_may_only_drive_GTxE4: The IBUFDS_GTE4 IBUFDS_GTE4 O pin may only be connected to the GTREFCLK pin of a GTHE4_COMMON, GTHE4_CHANNEL, GTYE4_COMMON, or GTYE4_CHANNEL component. The IBUFDS_GTE4 O pin cannot drive MMCME2_ADV. | 11:36 |
| tnt | ERROR: [DRC RTSTAT-1] Unrouted nets: 1 net(s) are unrouted. The problem bus(es) and/or net(s) are main_crg_clkin. | 11:36 |
| _florent_ | ok, you can try with the ODIV2 output | 11:45 |
| _florent_ | and set p_REFCLK_HROW_CK_SEL=0 to have ODIV2 = O | 11:47 |
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| tnt | Can litex configure the PS part to get its clock from there ? | 13:54 |
| tnt | (on a 10k$ dev board with thousands of IO, you would think they'd put a oscillator somewhere that's always running ....) | 13:54 |
| _florent_ | tnt: Have you been able to do a test with the PCIe clock? | 14:07 |
| tnt | _florent_: yeah, no luck either. I had to add a BUFG_GT after the IBUFDS_GTE4 for it to route, but still nothng. | 14:10 |
| tnt | I made a 'cloked' echo ( self.sync += serial_pads.tx.eq(serial_pads.rx) ) to be as simple as I could, and no joy. | 14:11 |
| tnt | I asked for configrmation that the board was indeed plugged into a PC, didn't get an answer yet. | 14:11 |
| _florent_ | for the Zynq, you can look at: | 14:12 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/cpu/zynq7000/core.py | 14:12 |
| _florent_ | and | 14:12 |
| _florent_ | https://github.com/antmicro/litex-rowhammer-tester/blob/master/rowhammer_tester/targets/zcu104.py#L69-L180 | 14:12 |
| _florent_ | tnt: otherwise, here is something I was doing on a 7-series board to use the clock from the configuration internal oscillator: | 14:18 |
| _florent_ | https://www.irccloud.com/pastebin/QIatcBGM/ | 14:18 |
| tpb | Title: Snippet | IRCCloud (at www.irccloud.com) | 14:18 |
| _florent_ | you can probably do something similar on Ultrascale | 14:19 |
| tnt | _florent_: tx, I'll give that a shot. | 14:24 |
| tnt | I got confirmation the board is in a pcie slot at least. | 14:24 |
| tnt | _florent_: \o/ Got to the bios prompt :) | 14:55 |
| tnt | I guess now the best would be to use that clock to configure the 120.88 MHz clock and actually use that as the system clock. | 14:56 |
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| _florent_ | tnt: great, so you used the STARTUPE3's CFGMCLK? | 15:17 |
| tnt | ATM I just let Xilinx remap the STARTUPE2 but I'll clean it up to E3 version. | 15:18 |
| tnt | Only difference is clock is 50MHz and not 65MHz | 15:18 |
| _florent_ | tnt: ok, as you were saying it's really a shame you don't have a valid input clock available from the PL for a board of this price :) | 15:19 |
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| G33KatWork | sajattack[m]: I did some yocto stuff for the Siglent scope, but it was all custom. We ditched everything Siglent did including the gateware, so at this stage it's pretty useless. We started building our own, but florent got way farther with LiteX than we did | 17:22 |
| G33KatWork | I also reverse engineered a good part of the hardware | 17:22 |
| sajattack[m] | ok good to know, thanks | 17:25 |
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| Wolf0 | G33KatWork: I'm working on doing that with Xilinx's HBM2 memory controller. It's a REALLY cool design | 17:58 |
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