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| benh | jevinskie[m]: in my case it works when using a LiteX SoC with VexRisc V and fails with the standlone LiteEth in microwatt... I think I got the constraints right (and there's no violation reported) but I'm crap at understanding Vivado timing reports | 00:52 |
|---|---|---|
| benh | LOL | 00:55 |
| benh | it would help if my vhdl wrapper for the core actually wired gtx :-) | 00:55 |
| benh | I can't believe I didn't get any warning | 00:55 |
| benh | interestingly enough, we don't generate any constraint for gtx | 00:55 |
| jevinskie[m] | I predicted it would be something simple :p | 01:03 |
| benh | and you were absolutely right :-) | 01:07 |
| benh | So... fun fact... yeterday QMtech told me that the speed grade was -1 | 01:26 |
| benh | but I noticed their manual says -2 | 01:26 |
| benh | and I just noticed, all their example projects are set for -2 | 01:26 |
| benh | I can't verify because it's a stupid QR-code only FPGA and Xilinx won't let me use the decoder... | 01:26 |
| benh | hrm | 01:28 |
| benh | they are confirming it's -1 and the manual and examples are wrong :-( | 01:28 |
| benh | and it seems the board V1 is also supposed to be -1 | 01:28 |
| benh | I've added a --speed-grade argument, I'm going to make it default to -1 | 01:29 |
| benh | ah... | 01:31 |
| benh | so they made 2 batches of board V1 | 01:31 |
| benh | one was -1 and one was -2 | 01:31 |
| benh | and board v2 is all -1 | 01:32 |
| benh | ok all good except... | 02:09 |
| benh | it doesn't always start properly after configuration with xc3progs | 02:09 |
| benh | I have to go long press the button that we connected to CPU reset and lift it | 02:09 |
| benh | then it starts | 02:09 |
| benh | something's not right with the reset logic | 02:09 |
| benh | after config | 02:10 |
| benh | works fine if flashed | 02:12 |
| benh | Melkhior: https://github.com/litex-hub/litex-boards/pull/273 (Wukong fixes & v2 support) | 02:17 |
| benh | _florent_: I also updated my liteeth "gen.py" fixes branch: https://github.com/enjoy-digital/liteeth/pull/81 | 02:20 |
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| Melkhior | benh: Most of them are -1 yet all the written documents say -2 ? That's not reassuring | 05:47 |
| Melkhior | benh: do you know if they have a way to tell the batch of a board ? | 05:48 |
| Melkhior | i don't remember double-checking, I just assumed they were telling the truth about the speed-grade ... | 05:50 |
| Melkhior | And the patch LGTM | 05:50 |
| jevinskie[m] | We need some back alley QR code scanning hah | 06:43 |
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| benh | Melkhior: yes, the QMtech guy told me "ooops ... we'll fix the doc" :-) | 07:35 |
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| emkat | I have extended the simsoc with a simple wb master which writes a single word to sdram when a bit in its CSR is set. I can see the wishbone transaction in the waveform after setting the CSR from the bios using mem_write, but I cannot read the value back with mem_read. I am suspecting this is a cache issue. I tried turning off the cache by specifying an L2 cache size of 0 and using the minimal variant of the cpu to no avail. How can I | 12:01 |
| emkat | make sure the cache is disabled or at least invalidated when I am trying to read back the value written by my custom wishbone master? | 12:01 |
| emkat | Update on my memory reading issue: PEBKAC. My master peripheral did not set the write enable signal. However, I am still puzzled by the output of csr.csv. Even after setting the L2 cache size to a different value (by using --l2-size in lxsim), I still see the default size of 8192 bytes for the l2_size config constant. I tried setting the l2 size to 32Ki, but it seemed to have no effect. | 12:30 |
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| mithro | Did I ever share https://github.com/rprinz08/hBPF ? We should totally get it integrated into LiteEth / https://github.com/litex-hub/linux-on-litex-vexriscv | 21:17 |
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