Friday, 2021-09-24

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benhjevinskie[m]: in my case it works when using a LiteX SoC with VexRisc V and fails with the standlone LiteEth in microwatt... I think I got the constraints right (and there's no violation reported) but I'm crap at understanding Vivado timing reports00:52
benhit would help if my vhdl wrapper for the core actually wired gtx :-)00:55
benhI can't believe I didn't get any warning00:55
benhinterestingly enough, we don't generate any constraint for gtx00:55
jevinskie[m]I predicted it would be something simple :p01:03
benhand you were absolutely right :-)01:07
benhSo... fun fact... yeterday QMtech told me that the speed grade was -101:26
benhbut I noticed their manual says -201:26
benhand I just noticed, all their example projects are set for -201:26
benhI can't verify because it's a stupid QR-code only FPGA and Xilinx won't let me use the decoder...01:26
benhthey are confirming it's -1 and the manual and examples are wrong :-(01:28
benhand it seems the board V1 is also supposed to be -101:28
benhI've added a --speed-grade argument, I'm going to make it default to -101:29
benhso they made 2 batches of board V101:31
benhone was -1 and one was -201:31
benhand board v2 is all -101:32
benhok all good except...02:09
benhit doesn't always start properly after configuration with xc3progs02:09
benhI have to go long press the button that we connected to CPU reset and lift it02:09
benhthen it starts02:09
benhsomething's not right with the reset logic02:09
benhafter config02:10
benhworks fine if flashed02:12
benhMelkhior: (Wukong fixes & v2 support)02:17
benh_florent_: I also updated my liteeth "" fixes branch:
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Melkhiorbenh: Most of them are -1 yet all the written documents say -2 ? That's not reassuring 05:47
Melkhiorbenh: do you know if they have a way to tell the batch of a board ?05:48
Melkhiori don't remember double-checking, I just assumed they were telling the truth about the speed-grade ...05:50
MelkhiorAnd the patch LGTM05:50
jevinskie[m]We need some back alley QR code scanning hah06:43
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benhMelkhior: yes, the QMtech guy told me "ooops ... we'll fix the doc" :-)07:35
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emkatI have extended the simsoc with a simple wb master which writes a single word to sdram when a bit in its CSR is set. I can see the wishbone transaction in the waveform after setting the CSR from the bios using mem_write, but I cannot read the value back with mem_read. I am suspecting this is a cache issue. I tried turning off the cache by specifying an L2 cache size of 0 and using the minimal variant of the cpu to no avail. How can I 12:01
emkatmake sure the cache is disabled or at least invalidated when I am trying to read back the value written by my custom wishbone master?12:01
emkatUpdate on my memory reading issue: PEBKAC. My master peripheral did not set the write enable signal. However, I am still puzzled by the output of csr.csv. Even after setting the L2 cache size to a different value (by using --l2-size in lxsim), I still see the default size of 8192 bytes for the l2_size config constant. I tried setting the l2 size to 32Ki, but it seemed to have no effect.12:30
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mithroDid I ever share ? We should totally get it integrated into LiteEth /
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