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| somlo | quad-core 64-bit rocket cpu with litex on nexys4ddr: https://hastebin.com/sopixegoye.yaml | 00:31 |
|---|---|---|
| tpb | Title: hastebin (at hastebin.com) | 00:31 |
| sajattack[m] | Congrats | 00:57 |
| sajattack[m] | How hard is it to port rocket linux to another litex board? | 00:57 |
| somlo | sajattack[m]: Thanks! Right now there are several boards known to work at github.com/litex-hub/linux-on-litex-rocket | 01:52 |
| somlo | smp support is just a matter of sufficient fpga capacity -- I'll post patches after I get some sleep :) | 01:54 |
| sajattack[m] | Only 5 I thought | 01:54 |
| somlo | it's all mostly upstream litex, if you look at the build command lines in the readme, so other boards *should* also work, only no one's tried yet | 01:57 |
| sajattack[m] | Cool I'll have to give it a shot | 02:53 |
| sajattack[m] | I've bumped into some problems with rv32gc support in various ways and curious to see if the grass is greener on the other side | 02:54 |
| sajattack[m] | initial results on my acorn_cle_215 pcie abomination..... the crossover `litepcie_util uart_test` reboots my pc | 03:25 |
| sajattack[m] | dma test works however | 03:27 |
| sajattack[m] | 2nd try is the charm? | 03:27 |
| sajattack[m] | https://hastebin.com/ufizehefuk.yaml | 03:27 |
| tpb | Title: hastebin (at hastebin.com) | 03:27 |
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| tpw_rules | sajattack[m]: have you had any issues with flaky compilation? it seems the basic litex examples only work on my nitefury if compilation is lucky | 03:50 |
| tpw_rules | i make small changes and then they break | 03:50 |
| sajattack[m] | I had a couple issues I guess | 03:55 |
| sajattack[m] | nothing major | 03:55 |
| sajattack[m] | somlo: I guess I need to write a dts? | 03:55 |
| tpw_rules | like what? i guess nitefury support seems kind of broken to me, but it's not great for you either | 03:57 |
| sajattack[m] | a couple times I had weird brokenness but I'm not sure if it was the compiler or pebkac | 03:57 |
| sajattack[m] | here goes nothing... | 04:29 |
| sajattack[m] | `[LXTERM] Uploading boot.bin to 0x80000000 (15698616 bytes)...` | 04:29 |
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| sajattack[m] | well that didn't work | 05:02 |
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| _florent_ | somlo: nice! | 06:35 |
| _florent_ | sajattack[m]: can you check the timings with Rocket @ 100MHz on the Acorn? | 06:35 |
| _florent_ | tpw_rules: the false path constraints have been updated on the Acorn design, can you provide more info on your failures? is it an issue with PCIe enumeration? or something else? | 06:36 |
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| Melkhior | somlo: awesome! how much resources are needed to get to dual-rocket or more? | 06:40 |
| Melkhior | _florent_: is there some standard way to 'remap'/'alias' some of the wishbone address space? The SDRAM is mapped as one contiguous block, but I need a small block (probably the last 1-8 MiB) read/writable at a different address for compatibility reasons | 06:42 |
| Melkhior | I can always had my own Wishbone slave + dedicated DRAM port, but it feels a bit overkill | 06:43 |
| Melkhior | TIA | 06:43 |
| _florent_ | Melkhior: We don't have this feature currently no, the custom DRAM port solution seems the way to go for now | 06:51 |
| Melkhior | OK thanks - might also try to 'remap' (in a somewhat hackish way) in my bridge, could be less resource-intensive | 06:55 |
| Melkhior | Another question - i see the Micro 4K uses GTPs for HDMI, where other board uses regular pins (and so there's 2 HDMI PHY for 7-series), any significant benefits to that? | 06:56 |
| Melkhior | kind of wondering if it's worth investigating for an hypothetical hdmi-enabled custom board | 06:57 |
| _florent_ | The main benefits is for high resolutions: regular Artix7 IOs can do up to 1.25Gb/s (so already overclocked at 1080p60/1.485Gbps), GTPs can do up 6.6Gbps, so are fine even for 4K | 07:06 |
| Melkhior | _florent_: OK so definitely worthwhile, even though GTPs are quite limited in numbers... would you expect any other change needed in HW design? | 07:12 |
| Melkhior | I was thinking of the Qmtech Wukong very simple design (https://github.com/ChinaQMTECH/QM_XC7A100T_WUKONG_BOARD/blob/master/Hardware/qmtech-xc7a100t-ddr3-wukong-board-v01.pdf, page 4) | 07:12 |
| Melkhior | (it seems the Mini 4k schematics are not public so I can't look at them for 'inspiration' :-) ) | 07:14 |
| _florent_ | The mini 4k has a 75dp159 between the GTPs and HDMI ports | 07:16 |
| Melkhior | _florent_: so more complex because I need level-shifters... thanks for the info | 07:29 |
| Melkhior | maybe 4K on a SPARCstation would be too ambitious, might have a go at lower resolution first :-) | 07:30 |
| geertu | Melkhior: That's only an improvement of 8x, compared to the original resolution ;-) And probably you go for increased color depth, too? | 07:34 |
| * geertu never noticed before that 1920 * 1080 = 2 * (1152 * 900) | 07:35 | |
| Melkhior | geertu: Not at first, I'm thinking of emulating a dumb cg3, plenty of sample codes out there (drivers & Qemu emulation) | 07:58 |
| Melkhior | also using 8 bits per pixels would save on memory bandwidth, so easier to use higher resolution | 07:58 |
| Melkhior | Of course eventually I would love to have a HW-accelerated 24-bits FrameBuffer with full X11 support, but that's a loooooooooooong way away :-) | 07:59 |
| Melkhior | (cg3 also have Forth OpenBIOS support so probably can get console support as well) | 08:01 |
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| acathla | The FOMU toolchain I was using doesn't like the new LDFLAGS in common.mak. What's the right toolchain to use? | 10:12 |
| _florent_ | acathla: you can use the one installed with LiteX: https://github.com/enjoy-digital/litex/blob/master/litex_setup.py#L67-L68 | 10:28 |
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| acathla | _florent_, Thanks, will be usefull but that didn't change anything... I changed $(LD) to $(CC) in my Makefile and it seems OK now. | 10:58 |
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| somlo | Melkhior: on the nexys4ddr, a single core (w/o gateware FPU) Rocket/Litex uses 32% of LUTs. A 4-core (FPU-less) setup goes up to 76% | 11:04 |
| david-sawatzke[m | florent: Could you take a look at the 32 bit mac PR in liteeth in the near future, please? I've used it quite a bit in the last few weeks (with the softcore) and it seems to work without issues. | 13:22 |
| david-sawatzke[m | I don't want to build too many future changes on these shaky grounds | 13:22 |
| Melkhior | somlo: thanks! that's on a A7-100T so it's not huge ; I don't think Rocket can share FPU between core the way VexRiscv can so adding FPUs might be difficult | 13:24 |
| Melkhior | But it's really great to have SMP RV64IMAC in Litex :-) | 13:25 |
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| hjimenez93[m] | Hi! I recently learned about LiteX, its awesome! I was wondering if you know of an existing or WIP open-source alternative to Xilinx' ERNIC IP for RDMA. | 13:30 |
| hjimenez93[m] | Btw, I learned about it in GRCon | 13:31 |
| somlo | Melkhior: I think the way it goes with Rocket is either all cores have FPUs or none do | 13:35 |
| somlo | there's room for 4-core FPU-enabled cores on the nexys-video or genesys2, but I haven't tried running anything there yet | 13:36 |
| somlo | s/cores/cpus/ | 13:36 |
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| Melkhior | somlo: That's the nice thing w/ VexRiscv - you can share a single FPU implementation between 1 or more core (AMD Bulldozer-like), so you get most of the benefits of HW FPU and a limited size impact | 13:45 |
| Melkhior | genesys 2 is a lot more expensive than A7-100T boards... | 13:46 |
| Melkhior | Maybe dual-core RV64GC would fit? FPUs aren't that big... | 13:47 |
| somlo | Melkhior: the cool thing about the genesys2 is that a quad-core rocket litex design (with gateware FPUs) passes timing at 100MHz (as opposed to 50, like everywhere else so far) | 13:48 |
| somlo | which should be exciting, once I get around to running it | 13:48 |
| Melkhior | Yes, the 2x freq increase sounds good :-) | 13:48 |
| Melkhior | Wonder how many rockets would fit in a VCU128 and at what speed - the HBM sure would be able to supply enough bandwidth :-) | 13:50 |
| somlo | you could try to build it with variant `full4d` or `full4q` and see what the utilization percentage is... Then we could create a variant with more cores (linux currently supports up to 8, but even that could probably be increased) | 13:56 |
| somlo | s/linux supports/the current linux litex rocket defconfig supports/ | 13:56 |
| somlo | to be precise... | 13:57 |
| Melkhior | I suspect the 8 hart limit might be in OpenSBI as well | 13:57 |
| Melkhior | Anyway rhetorical question, HBM is not yet supported, the VCU128 is not yet supported, and mine is for 'real work' only :-/ | 13:59 |
| Melkhior | You can fit a lot of stuff in that FPGA :-) | 13:59 |
| gatecat | hmm, I've got the Alveo U250, but I think some work would be needed to take advantage of more than one DDR4 channel (and I don't think we got DDR init entirely reliable on all channels either) | 14:00 |
| * somlo is dreaming of the day one could just use yosys+nextpnr on it directly :) | 14:00 | |
| Melkhior | yosys+nextpnr on the Artix-7 and DDR3 at a good level of performance would be a great starting point before moving to Kintex and HBM :-) | 14:02 |
| somlo | pythondata-cpu-rocket has 4-core variants with and without gateware FPU, and the provisional litex support is in PR 1040, if any of you want to tinker with it | 14:02 |
| Melkhior | somlo: if only I had the time :-/ the little I have I waste on SBusFPGA at the moment | 14:03 |
| somlo | Melkhior: speaking of, I'm going to grudgingly stop this for today and start paying attention to my $DAYJOB :D | 14:04 |
| Melkhior | hehe :-) | 14:04 |
| Melkhior | thanks for the SMP stuff!! | 14:05 |
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| _florent_ | david-sawatzke[m: sorry yes I'll try to review and merge it this week | 16:37 |
| _florent_ | hjimenez93[m]: Hi and welcome :) (Personnaly, I'm not aware of ERNIC IP open source alternative). | 16:41 |
| _florent_ | gatecat: for the Alveo U250, the easy way to integrate the 4 DDR channels is to have 4 standalone LiteDRAM core (each itself being a SoC) and another top level SoC doing the integration | 16:45 |
| _florent_ | gatecat: I already have this running on the XCU1525 | 16:46 |
| _florent_ | gatecat: when using a small CPU, the extra resources used by the standalone core is negligible | 16:48 |
| _florent_ | gatecat: and that's in fact very similar to the MIG that embeds a Microblaze for each controller :) | 16:48 |
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| mm001 | I'm still trying to figure out why the rgmii_test.py of the chubby75 project crashes on an incoming udp packet while the linsn_rv901t.py from litex-hub does not. | 20:20 |
| mm001 | Apart the sys_clk_freq, I don't really see a difference for the ethernet phy... | 20:20 |
| mm001 | By the way, if I change the sys_clk_freq from 133e6 to 75e6 in rgmii_test.py, it doesn't work at all, can't even get a ping response. | 20:21 |
| mm001 | But I can't see why the sys_clk_freq should work at 75e6 with linsn_rv901t.py when it does not with rgmii_tes.py | 20:23 |
| mm001 | Could that also be related to the crash on incoming udp packet? | 20:24 |
| *** peeps[zen] is now known as peepsalot | 20:59 | |
| jevinskie[m] | You could probably fit a "couple" of rocket cores on this 480k LE Arria 10 board you can get for ~$150 USD. 👀 Anybody happen to have schematics? https://www.ebay.com/itm/174944904362 | 21:16 |
| tpb | Title: GIBEL HawkEye-20G -48 ALTERA Arria 10 FPGA Computation Accelerator 2SFP 4GBDDR4 | eBay (at www.ebay.com) | 21:16 |
| * sajattack[m] posted a file: (1767KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/hAmtAfZcsTvZbfYVsezSqzFu/sqrl_acorn_timing.rpt > | 21:20 | |
| sajattack[m] | <_florent_> "sajattack: can you check the..." <- ☝️ | 21:20 |
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