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| mithro | gatecat: There is a reason that timvideos/litex-buildenv uses a separate build directory based on cpu type + variant | 00:19 |
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| mikek_DE1SOC | test test | 13:05 |
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| _florent_ | Hi, with https://github.com/enjoy-digital/litex/commit/44b223a9182318d58b9d4249d879f925dfd11e7d, the BIOS/libs will now be fully rebuilt on CPU type/variant change | 13:41 |
| cr1901 | _florent_: Is this still possibly of any use for you? https://github.com/cr1901/libmodem/blob/master/scripts/misoc-config.py (litex-config.py) | 13:55 |
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| vomoniyi[m] | Hi everyone, I just tried to load the kernel module. When I check the dmesg, I get this error log. Anyone know what the problem is? https://pastebin.com/Ez5vGTSp | 14:20 |
| tpb | Title: [ 891.787304] litepcie 0000:01:00.0: Unsupported device version 255[ 891.787 - Pastebin.com (at pastebin.com) | 14:20 |
| a3f | vomoniyi: power cycling the device worked for me | 14:23 |
| _florent_ | cr1901: Sorry I've still not been able to look at it, I'll try to do it soon (so can't answer for now) | 14:30 |
| _florent_ | vomoniyi[m]: do you see you board with LitePCIe? Which design are you building? | 14:32 |
| vomoniyi[m] | No I don't and I'm building the litex build of the sqrl acorn target | 14:38 |
| vomoniyi[m] | Wait, yes I can see it in litepcie | 14:45 |
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| Wolf0 | _florent_: I'm also interested in whatever you might be doing with the HBM2 (if it might be improved by better speeds, for example?) | 18:58 |
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| tpw_rules | hello all. i have a nitefury board i'm trying to get the litex boards example to work on | 20:46 |
| tpw_rules | i installed litex and ran the "./sqrl_acorn.py --uart-name=crossover --with-pcie --build --driver --load --variant=cle-215" but vivado eventually dies with "ERROR: [Vivado 12-5201] set_clock_groups: cannot set the clock group when only one non-empty group remains." | 20:47 |
| tpw_rules | vivado 2020.2 and python3.9.1 on ubuntu 20.04 is what i am using | 20:47 |
| tpw_rules | full log: https://pastebin.com/PV8uQr2H | 20:51 |
| tpb | Title: INFO:SoC: __ _ __ _ __ INFO:SoC: / / (_) /____ | |/_/ - Pastebin.com (at pastebin.com) | 20:51 |
| tpw_rules | do i need an older vivado? | 21:10 |
| tpw_rules | hm, 2019.2 dies with something about XML schema validation | 21:30 |
| zyp | I've used 2019.2 before | 22:00 |
| zyp | (to build for cle-215) | 22:01 |
| tpw_rules | that's strange. do you recall what commits you used? the litepcie phy files only changed 11 months ago | 22:02 |
| zyp | no, I don't, but it might be more than 11 months ago :) | 22:10 |
| tpw_rules | a3f: i see you have an issue filed on litepcie where you got this working, what vivado are you using? are you using the latest version of all the litex code? | 22:20 |
| tpw_rules | ahhh, the problem is trying to use the crossover uart | 22:30 |
| tpw_rules | but i don't have a real uart available... what voltage are the uart pins on the board? is there a way to use one over jtag? | 22:30 |
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