Sunday, 2021-08-22

*** tpb <[email protected]> has joined #litex00:00
*** Degi_ <[email protected]> has joined #litex00:35
*** Degi <[email protected]> has quit IRC (Ping timeout: 252 seconds)00:36
*** Degi_ is now known as Degi00:36
*** alainlou <[email protected]> has quit IRC (Ping timeout: 246 seconds)03:07
*** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.)05:10
*** TMM_ <[email protected]> has joined #litex05:10
*** Coldberg <[email protected]> has quit IRC (Ping timeout: 252 seconds)05:23
*** Abhishek_ <[email protected]> has joined #litex07:22
*** Coldberg <[email protected]> has joined #litex09:54
*** Abhishek_ <[email protected]> has quit IRC (Quit: Connection closed for inactivity)10:47
david-sawatzke[malainlou: FYI, I've found an example for storing the bios in the external spi flash: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/targets/muselab_icesugar.py11:04
*** futarisIRCcloud <[email protected]> has quit IRC (Quit: Connection closed for inactivity)11:15
*** alainlou <[email protected]> has joined #litex14:53
MelkhiorThe awesome power of Litex: https://www.reddit.com/r/vintagecomputing/comments/p98pl1/sparcstation_20_with_fpgabased_256_mib_ddr3_ram/14:53
_florent_mithro: Scalenode seems interesting, I also bought some hardware some time ago to build to create a local regression bench but haven't set it up yet16:16
_florent_Melkhior: Nice, thanks for sharing16:17
Melkhior_florent_: thanks for Litex :-)16:20
MelkhiorBTW for the cheap DECA board, there's a controller now: https://www.eevblog.com/forum/fpga/brianhg_ddr3_controller-open-source-ddr3-controller/16:21
tpbTitle: BrianHG_DDR3_CONTROLLER open source DDR3 controller. - Page 1 (at www.eevblog.com)16:21
Melkhiorversion 1.0 should land soon16:22
alainlouthanks david-sawatzke[m! I'll need to have a look!16:47
alainlouhappy sunday everyone! sorry to disturb but I'm kinda stuck on a problem and would appreciate any help! https://github.com/litex-hub/litex-boards/issues/253#issuecomment-90330191517:38
Melkhioralainlou: looks like a speed mismatch, but I guess you already double-checked the settings on lxterm ? (as you've clearly checked on the UART size!)17:47
Melkhioryou might want to try minicom just to be sure17:48
Melkhiors/size/side/17:48
alainlouhey Melkhior, thanks for the tip - yea unfortunately I get the same problem :(18:57
*** TMM_ <[email protected]> has quit IRC (Quit: https://quassel-irc.org - Chat comfortably. Anywhere.)20:37
*** TMM_ <[email protected]> has joined #litex20:37
jevinskie[m]What’s the name for the ddr3l mode where everything is done single data rate?21:08
tntslow ?21:41
Wolf0_florent_: nice! thanks!22:39
Wolf0I've tried it on four FPGAs so far, three boards (one board is dual-FPGA)22:39
Wolf0Only one of them takes 1200Mhz on the HBM2. :322:39
Wolf0https://twitter.com/Wolf9466/status/142693519299704832122:40
jevinskie[m]tnt: yeah but also perhaps simpler and lower latency :)23:59

Generated by irclog2html.py 2.17.2 by Marius Gedminas - find it at https://mg.pov.lt/irclog2html/!