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| promach[m] | how is the PLL dynamic phase shift feature of litedram on spartan-6 being configured ? | 02:10 |
|---|---|---|
| promach[m] | https://forums.xilinx.com/t5/FPGA-Configuration/PLL-dynamic-phase-shift-approach/m-p/1274075/highlight/true#M23870 | 02:10 |
| tpb | Title: Re: PLL dynamic phase shift approach - Community Forums (at forums.xilinx.com) | 02:10 |
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| shiva12 | Hi Team, | 04:48 |
| shiva12 | In the ASIC point of view which is the best one, Litex-VexRiscv or Rocket chip? | 04:48 |
| shiva12 | Is there any documentations available for the comparison of these two? I am a bit confused about these two cores. | 04:48 |
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| geertu | shiva12: vexriscv is rv32, rocket is rv64 | 06:40 |
| shiva12 | from the asic point of view which is good | 06:42 |
| geertu | shiva12: I can't comment on the ASIC PoV, but if you plan to run an official Linux distro, you want rv64. | 06:59 |
| shiva12 | okay | 07:21 |
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| OmkarBhilare[m] | has anyone used wb_cti in your design to access wb port on litex | 15:51 |
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