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| rom | I think external Wishbone/AXI for my application is ok, since I will also generate the clock from FPGA | 01:34 |
|---|---|---|
| promach[m] | <_florent_ "On Spartan6 we are using a fixed"> fixed phase shift as in `rd_bitslip = 1` which means a 360 degree phase delay ? | 01:39 |
| promach[m] | _florent_: | 01:39 |
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| _florent_ | promach[m]: For the value of wr/rd_bitstlip in the example code I provided, the hardware and rest of the code also needs to be considered. This was more an example of values that needs to be manually adapted | 07:55 |
| _florent_ | You can see that these values are different between hardware: | 07:55 |
| _florent_ | https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/galatea/base.py#L214-L216 | 07:56 |
| _florent_ | https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/opsis/base.py#L287-L289 | 07:57 |
| _florent_ | https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/pipistrello/base.py#L222-L224 | 07:57 |
| _florent_ | https://github.com/timvideos/HDMI2USB-litex-firmware/blob/master/targets/waxwing/base.py#L206-L208 | 07:58 |
| _florent_ | I'm not saying that's necessarily the way to go but the way we did it in the past on Spartan6 :) (That has been improved since then with software auto calibration on 7-Series/Ultrascale). | 07:59 |
| promach[m] | _florent_: cool, I was thinking about using PLL dynamic phase shift feature before you mentioned about bitslip delay | 08:23 |
| _florent_ | promach[m]: In fact you can see phase shift as a fine delay (adjusting sampling delay) and bitstlip as a coarse delay (adjusting bit order in the deserialized data) | 08:25 |
| promach[m] | _florent_: may I know if you also used PLL dynamic phase shift feature together with bitslip for spartan-6 ? | 08:37 |
| _florent_ | promach[m]: no we manage to get it working without, but dynamic phase shift can provide you more flexibility | 08:39 |
| promach[m] | does spartan-6 use both fine delay and course delay ? | 08:39 |
| _florent_ | fine delay was done using fixed phase shift of the clocks with the PLL and coarse delays with the bitslio | 08:43 |
| _florent_ | bitslip | 08:43 |
| promach[m] | <_florent_ "fine delay was done using fixed "> _florent_: you mean on spartan-6, the fine delay is calibrated during the **initial read calibration** , and then is fixed during actual read operations ? | 08:47 |
| _florent_ | promach[m]: yes, and the calibration was done manually | 08:49 |
| * promach[m] uploaded an image: (53KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/GOnspzoJjVVvQXhVayaQoZEV/image.png > | 09:01 | |
| promach[m] | _florent_: I am reading up on fixed phase shift in https://www.xilinx.com/support/documentation/user_guides/ug382.pdf#page=65 | 09:01 |
| promach[m] | is this what is being used on spartan-6 ? | 09:02 |
| promach[m] | _florent_: strange, I do no see any attribute named as "PHASE_SHIFT" | 09:24 |
| * promach[m] uploaded an image: (130KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/ELEwNKEtGjNexAopWCNFikZc/image.png > | 09:24 | |
| _florent_ | the phase is applied on CLK_OUTN outputs | 10:22 |
| promach[m] | <_florent_ "the phase is applied on CLK_OUTN"> you mean **CLKOUTn_PHASE** ? | 10:39 |
| promach[m] | as inside the PLL_BASE Settings page ? | 10:39 |
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| _florent_ | promach[m]: In fixed mode, the phase is configured through the CLKOUTN_PHASE attributes, in dynamic mode through the DRP interface and phase shift is then present on CLK_OUTN outputs | 12:01 |
| promach[m] | _florent_: I suppose litedram is not using dynamic mode for spartan-6 ? | 12:07 |
| promach[m] | and what do you mean by DRP interface ? | 12:09 |
| promach[m] | Do you mean DCM_SP Settings instead ? | 12:09 |
| * promach[m] uploaded an image: (128KiB) < https://libera.ems.host/_matrix/media/r0/download/matrix.org/PMONsdpunnJjPqihoyYyFTrO/image.png > | 12:10 | |
| promach[m] | there is also PHASE_SHIFT attribute inside DCM_SP Settings page | 12:10 |
| promach[m] | and CLKOUT_PHASE_SHIFT can choose between VARIABLE and FIXED | 12:10 |
| promach[m] | I am bit confused now | 12:12 |
| DerekKozel[m] | _florent_: I have a built image, programmed both by openocd (I think successfully) and by Vivado's hardware manager, I've built and loaded the litepcie kernel module and it shows as loaded. However the only output in dmesg is | 12:48 |
| DerekKozel[m] | > [ 658.091296] litepcie: loading out-of-tree module taints kernel. | 12:48 |
| gatecat | is anything showing up in lspci ? | 12:49 |
| DerekKozel[m] | litepcie_util info says it Could not init driver | 12:49 |
| DerekKozel[m] | lspci originally showed the SQRL blah blah blah at 0000:00:01.0 | 12:50 |
| DerekKozel[m] | now it does not show the device | 12:50 |
| gatecat | you might want to try a rescan as per https://github.com/enjoy-digital/litepcie/issues/36 ? | 12:50 |
| DerekKozel[m] | when I print the verbose tree that node shows as blank | 12:50 |
| gatecat | beware, I've locked up machines doing this | 12:50 |
| DerekKozel[m] | Thankfully working on a separate machine | 12:51 |
| DerekKozel[m] | the rescan did not seem to produce a useful result | 12:51 |
| * DerekKozel[m] < https://libera.ems.host/_matrix/media/r0/download/libera.chat/3bce10288389403ddb0d4302c45a9916455cd925/message.txt > | 12:52 | |
| gatecat | yeah, not much sign of anything showing up :/ | 12:52 |
| DerekKozel[m] | I had this all working last year when I was using a Thunderbolt adapter, should have written more notes! | 12:54 |
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| rom | Hi | 16:12 |
| rom | I want to ask about the --with-wishbone-memory option for VexRiscV-SMP | 16:12 |
| rom | what does it do exactly? Because afaik, if it's true then the core itself won't generate the LiteDRAM bus and do nothing after that | 16:12 |
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| OmkarBhilare[m] | We had produced the litex core with serv+litedram with this target file https://github.com/BeagleWire/litex-boards/blob/beaglewire-mw/litex_boards/targets/beaglewire.py | 17:40 |
| OmkarBhilare[m] | I wanted to put a user wishbone port so I can connect some other logic with the sdram. | 17:41 |
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| rom | OmkarBhilare[m]: Hey, you have (almost) the same goal as I do, for me it's to connect the SDRAM itself | 17:49 |
| _florent_ | DerekKozel[m]: sorry I'm leaving the office but could provide you a "known to work" bitstream for the Acorn tomorrow morning | 17:52 |
| _florent_ | rom: with "--with-wishbone-memory" VexRiscv-SMP is connected to the main bus of the SoC which is then connected to LiteDRAM | 17:54 |
| _florent_ | rom: without, VexRiscv-SMP each core has 2 direct interfaces connected to LiteDRAM | 17:55 |
| rom | _florent_: So that is the exact use case that you told me yesterday, "configure VexRiscv-SMP to use the Wishbone interface", if I understand it correctly? | 17:56 |
| _florent_ | OmkarBhilare[m]: you can use what I was describing yesterday to rom: https://github.com/enjoy-digital/litex/blob/master/litex/tools/litex_gen.py#L133-L139 | 17:56 |
| _florent_ | rom: exactly | 17:56 |
| _florent_ | sorry I have to go | 17:57 |
| rom | _florent_: thank you for the big help! | 17:58 |
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| DerekKozel[m] | _florent_: thanks. That'd be useful to ensure that my problems are "limited" to UEFI signing (Seems to work) and PCIe re-enumeration | 19:34 |
| DerekKozel[m] | I'm trying to get the base example gateware working so vomoniyi can take it forwards with developing some new features. | 19:36 |
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