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| tnt | Hi. I'm looking at linux.config in linux-on-litex-vexriscv and I see CONFIG_SMP is y ? Is that expected for a single cpu riscv setup ? | 06:46 |
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| shoragan | tnt, litex supports generating multicore vexriscv | 06:51 |
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| Finde | SMP doesn't mean there necessarily are multiple cores, just that they're supported | 06:58 |
| tnt | yeah, I just wasn't sure if the CSR (or alike) used to even detect multiple cores would be supported in a single core vex. | 07:02 |
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| tnt | Somewhat related question : Anychance of running linux on rv32 without atomics ? | 09:06 |
| gatecat | tnt: I don't recommend this but I have done it... https://github.com/daveshah1/litex-linux-riscv/commit/a9819e66989207b09205311459340472dcf3519c | 09:24 |
| gatecat | doing the emulation in M-mode would be cleaner | 09:24 |
| tnt | gatecat: Oh nice, thanks ! | 09:32 |
| tnt | ATM I'm just trying to get things vaguely doing something ... but DCache is too large and AFAICT Vex doesn't support AMO without DCache. | 09:33 |
| leons | I've been working on getting LiteX to work on some FPGA board, and unfortunately I'm again at the point where I have issues with DRAM and no clue really on how to diagnose these. | 09:42 |
| leons | Logs and definitions: https://gist.github.com/lschuermann/9a748ad2d8904d5a4bf9361f4b37485d | 09:42 |
| leons | Weirdly enough, my DRAM memory seems to work but the memtest is still "KO" | 09:42 |
| tnt | "best: m2, b04 delays: -" sounds bad to me | 09:44 |
| tnt | looks like one of the group failed training | 09:44 |
| leons | tnt: Ah, right, I see that now. I should probably check the constraints then, right? Is there any signal to watch out for specifically? | 09:47 |
| tnt | DQS maybe. | 09:49 |
| tnt | but really I think a wrong DQ would also cause it so . | 09:49 |
| gatecat | yeah | 09:49 |
| gatecat | DQS, DQ and DM | 09:50 |
| gatecat | for m02, the third group | 09:50 |
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| leons | Woah cool, the second DRAM module works perfectly! Will check the constraints of the first now. | 10:45 |
| leons | It's really tedious so I've been whipping up a small python script to translate the MIG XML files to LiteX constraints :) | 10:45 |
| leons | With at least one of my DRAM modules running, I'm reaching speeds of approx. 30MiB/s write and 26MiB/s read. The reference of my FPGA board claims that the DRAM can run at 800MHz and my board features a 233.3MHz clock signal to be used by the MIG. Does LiteDRAM support running the memory at higher speeds, through an external clock? | 12:07 |
| _florent_ | leons: The speed reported by the BIOS is the speed seen by the CPU (with the CPU/Wishbone being the bottleneck) | 12:12 |
| leons | florent: Ah, right, I suspected that already | 12:14 |
| _florent_ | if you want to test with a hardware generator/check, you can enable the BIST module by setting with_bist=True in add_sdram | 12:14 |
| _florent_ | https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc.py#L1225 | 12:14 |
| _florent_ | you'll then have a sdram_bist command available in the BIOS | 12:14 |
| _florent_ | the issue with your first DRAM could be related to a missing INTERNAL_VREF or DCI_CASCADE property | 12:17 |
| _florent_ | ex: https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/digilent_genesys2.py#L162 | 12:17 |
| _florent_ | https://github.com/litex-hub/litex-boards/blob/master/litex_boards/platforms/xilinx_kc705.py#L554 | 12:17 |
| _florent_ | make sure to apply/user the ones you'll find in the MIG | 12:18 |
| _florent_ | apply/use | 12:21 |
| leons | Ah, thanks. I can confirm that works, unfortunately getting a ton of errors which I suppose isn't expected :) | 13:03 |
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| leons | _florent_: I'm afraid I think the MIG generates for both INTERNAL_VREF and DCI_CASCADE the value 0, which is not translated into a constraint | 14:39 |
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| Melkhior | leons: there were discussions about DRAM speed in Litex here: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/229 | 15:57 |
| Melkhior | One Vexriscv can't saturate anywhere near DDR3 bandwidth, even using native interface (i.e. not going through Wishbone) | 15:58 |
| Melkhior | I've seen 100+ MB/s with 4 cores using 1 (shared by 4 cores) or 2 (shared by 2 cores each) FPUs on the 'normal' STREAM benchmark (which is using FP64) | 15:59 |
| Melkhior | And even 170+ MB/s using hand-tuned assembly in the critical loop | 16:00 |
| Melkhior | That's with a 100 MHz sysclk and a 16-bits device (400 MHz DDR3) | 16:01 |
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| leons | Melkhior: thanks for the pointer! I'm still pretty new to this stuff... | 17:07 |
| leons | Eventually I'd like to access the memory in hardware anyways, but for now it's a good first milestone to get the memory working at all :) | 17:07 |
| leons | With AXI lite I'm getting about 600MiB/s in both directions, which isn't too bad but nowhere near the theoretical limit | 17:08 |
| leons | (That's in hardware of course, with `sdram_bist`) | 17:09 |
| Melkhior | leons: that's already pretty impressive! | 17:11 |
| leons | Melkhior: But with a 64-bit 800MHz DDR3 | 17:11 |
| Melkhior | leons: whoa that's a big memory for a FPGA | 17:11 |
| leons | Yeah, the FPGA is pretty OP, 2x4GB and Virtex7 690T. Not mine, of course :) | 17:12 |
| Melkhior | That's not-so-old laptop territory already... | 17:12 |
| Melkhior | Hehe, yes I also have a 'big' one but it's for work only :-) | 17:13 |
| Melkhior | Fun stuff can make do with an Artix-7 | 17:14 |
| leons | Absolutely. | 17:14 |
| leons | _florent_: Is a basic SoC with UART, LEDs, Buttons and one of the SO-DIMMs sufficient for an initial upstream already or should I try to get both memories and the Ethernet working first? | 17:15 |
| leons | I'm also thinking about trying to wire a MIG-generated memory up to the AXI lite bus, just to find out whether my hardware is borked or I'm doing something wrong with LiteDRAM (probably the latter) | 17:16 |
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