Wednesday, 2021-07-21

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mithroI just discovered https://aignacio.com/posts/hdls/mpsoc_riscv/03:30
tpbTitle: How to fit 100x RISC-V cores into an FPGA | aignacio (at aignacio.com)03:30
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_florent_mithro: thanks, I also discovered this a few days ago. The NoC part seems really interesting10:36
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chiefwigmsany luck w/ ultrascale+ liteeth?12:55
chiefwigms:)12:55
OmkarBhilare[m]Do we have any Cpu Non litedram example with external initialization?15:05
OmkarBhilare[m] * Do we have any Cpu None litedram example with external initialization?15:05
mithrochiefwigms: I would have thought someone had already done that?15:33
chiefwigms_florent_ added some code a few days ago, (i tried testing it with a kcu116 and autogenerated code that I had) - but it seems like nothing gets added in the device tree source for new eth phys15:48
chiefwigmsnot sure if that is the only issue, or if more work needs to be done getting the core up as well15:48
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_florent_mithro: chiefwigms want to use 1000-BaseX on a Ultrascale+, 1000-BaseX has only been validated on 7-series and Ultrascale for now16:05
_florent_I just did a skeleton a few days ago: https://github.com/enjoy-digital/liteeth/commit/2f4964cf56fd5258eda21448269924da0821bfca and verified compilation but haven't been able to investigate further16:06
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Melkhior<OmkarBhilare[m]: what do you mean, initiliazing litedram without a CPU in the SoC ?17:26
_florent_Melkhior: With SDRAM the initialization is very simple (just a few MR registers to write) so the CPU doing the initialization can be easily replaced with a simple FSM doing Wishbone accesses to the DFI interface17:43
OmkarBhilare[m]Where can I find more info on these MR registers?17:44
_florent_Generally the CPU is used after the DRAM initialization to run software, so comes for free for the intialization, but when the CPU is only used for DRAM init, it could be interesting to replace it with an FSM17:45
_florent_OmkarBhilare[m]: Here is some code I was using for this (but for DDR3 with fixed bitslips/delays for the read leveling): https://gist.github.com/enjoy-digital/529a4d9994f0cc95e45382e4eb253b0917:56
_florent_It should be easy to adapt it to SDRAM17:56
_florent_You mostly have to adapt the init sequence17:57
_florent_to use this one: https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L33-L4117:58
_florent_you can generate the init sequence as pseudo code with this: https://github.com/enjoy-digital/litedram/blob/master/litedram/init.py#L821-L84617:58
_florent_sorry I have to go17:59
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Melkhior_florent_: you mean non-DDR sdram right? DDR3 is not so trivial... I tried porting the BIOS code to Forth (for OpenBoot/OpenFirmware) but have yet to succeed18:28
MelkhiorI have fallen back of regular C code in the OS driver (as it's used as a peripheral by another host)18:29
MelkhiorOh, that gist is for DDR3... i'll have to look into that18:30
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Guest12Are there any limitations on the refresh interval in litedram?  I've made some changes to tREFI that apparently are being ignored19:55
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leonsI have an FPGA board which has some logic level converters on IOs such as the UARTs. I'm currently just initializing (setting IO directions and output enable) in the BaseSoC construtor in the target file20:02
leonsIs that the right place to do this or is there some better way?20:02
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