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| dcallagh | does anyone know how to populate initial values for LRAM in Radiant Verilog? | 08:41 |
|---|---|---|
| dcallagh | the litex.soc.cores.ram.lattice_nx.NXLRAM class doesn't know how to do that currently, but i'm trying to add it, so that i can place BIOS in an LRAM and execute from it | 08:42 |
| dcallagh | seems like the Verilog module for the LRAM takes a long sequence of parameters like `INITVAL_00` .. `INITVAL_7F` containing a 640-byte hex string | 08:43 |
| dcallagh | but i can't find any docs from Lattice about the exact meaning of those parameters | 08:43 |
| dcallagh | gatecat: it looks like you have implemented support for those parameters in yosys/prjoxide, do you know if there is any docs for them or how exactly i can use them? | 08:44 |
| dcallagh | i'm too much of a noob to understand what the code in prjoxide is actually doing with those parameters | 08:45 |
| gatecat | The Verilog code that configures them in Yosys is https://github.com/YosysHQ/yosys/blob/master/techlibs/nexus/lrams_init.vh and https://github.com/YosysHQ/yosys/blob/master/techlibs/nexus/lrams_map.v#L34 | 08:46 |
| tpb | <https://x0.no/4uxdq> (at github.com) | 08:46 |
| gatecat | each 40 bits of each init string is actually used only for 32 bits with 8 bits of padding | 08:47 |
| gatecat | I don't know why this is, but I'm sure it made sense to someone at Lattice | 08:47 |
| dcallagh | ha. okay. so i can fill those parameters with 32 bits of real data and 8 bits of zeroes alternating? | 08:48 |
| gatecat | yeah, that seems like what I worked out... | 08:48 |
| dcallagh | that explains why 640*0x80 adds up to 80KB but the LRAM is only 64KB | 08:48 |
| gatecat | right | 08:48 |
| dcallagh | okay. tomorrow i'll try feeding that to radiant and see what happens. thanks | 08:49 |
| dcallagh | am i right in assuming that Lattice do not document this anywhere? | 08:49 |
| dcallagh | they expect everyone to just design their stuff in Radiant GUI with pointy-clicky and leave their Verilog modules totally undocumented? | 08:49 |
| dcallagh | the Radiant GUI offers to fill in an initial value into LRAM for me but that obviously doesn't help Litex generating Verilog | 08:50 |
| gatecat | yeah I don't think there are any good Lattice docs about this | 08:52 |
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| zyp | _florent_, boards for the stuff I've been working on have arrived and things are starting to fall into place: https://bin.jvnv.net/file/XHzyw.jpg https://bin.jvnv.net/file/IvGDv.png :) | 18:13 |
| zyp | for now I've copied Greg's hyperram init code and patched that into the bios, but I wonder what would be the reasonable way forward with that? | 18:18 |
| zyp | should I just add a liblitehyperbus in the same style as the other init codes, or would you like me to make a proposal for how to hook code into the bios without being part of the litex repo itself? | 18:20 |
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