Thursday, 2019-07-18

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carlatwin(LX P=arty C=mor1kx) [email protected]:~/lhub/litex-buildenv$ uname -a00:48
carlatwinLinux DESKTOP-KOJ4LVF 4.4.0-17763-Microsoft #379-Microsoft Wed Mar 06 19:16:00 PST 2019 x86_64 GNU/Linux00:48
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xobsWhat's the best way to mux io pins in litex?  I'm looking to interleve a hardware SPI block with `spi_flash`, and it seems like that's almost doable.05:52
xobsThe problem being that the SPI pins are bidirectional.  In SpiFlashDualQuad they use a TSTriple.  Is there something that exists that fakes that to let me mux it?05:53
keesjhmmm06:56
keesjI don't understand the faking part.06:57
xobsI guess what I'm looking to do is hand SpiFlash a "Pad-ish" object that it could pass to TSTriple, but that I could disconnect and hand over to a different block instead.06:58
xobsIn a CPU, you can usually mux one pin between behaviors and the blocks themselves don't care about what's going on in the outside world.06:59
keesjI think... I am currently also working on something with bidirectinal pins and I copied code from litedram 's code base07:00
keesjthis uses the special block. I think you are looking for an abtraction of a bidirectional pin07:00
xobsYeah, one option is to redo it so that it accepts an "in", "out" and "oe" pins instead of a "Pad".07:01
xobsI'm wondering if such a thing exists already.07:02
keesjI am seraching .. I had something like that yesterday07:03
xobsThough, maybe it makes sense to change the SpiFlash() constructor to accept a Module that could be overriden for fancier bitbanging.07:03
keesjby itself this is already supported in verilog (setting the port to high impedence) ( https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi_flash.py indeed uses TSTriple)07:10
tpbTitle: litex/spi_flash.py at master · enjoy-digital/litex · GitHub (at github.com)07:10
keesjis https://github.com/m-labs/migen/blob/master/migen/fhdl/specials.py#L52 Tristate note enough?07:10
tpbTitle: migen/specials.py at master · m-labs/migen · GitHub (at github.com)07:10
keesjI am used to grepping code but for language type constructs I think a good reference manual would certainly help07:11
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_florent_xobs: there is no pre-existing module to do that07:40
_florent_but if you define pads like this: pads = Record([("clk", 1), ("cs_n", 1), ("dq_o", 4), ("dq_i", 4), ("dq_oe", 1)])07:41
_florent_and then in SPIFlash, so something like this:07:41
_florent_https://www.irccloud.com/pastebin/xoImrr0n/07:41
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)07:41
_florent_sorry, like this:07:42
_florent_https://www.irccloud.com/pastebin/UpzsO4fn/07:42
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)07:42
_florent_then you will be able to put the TSTriple outside07:42
xobs_florent_: that looks like an interesting (and clever) approach, thanks!07:43
_florent_but the actual SPIFlash is indeed not easy to modify, i'd like we make it more generic and easy to modify07:43
_florent_your idea about having a specific module for the bitbang logic and pass it as a parameter was also interesting and could ease readibility07:48
_florent_in fact maybe we should remove the bitbang logic from SpiFlashDualQuad/SpiFlashSingle07:48
_florent_create SpiFlashDualQuadBitbang/SpiFlashSingleBitbang modules07:49
xobsThat's what I'm thinking.  Or something similar.07:49
xobsRight now I'm looking into what it would take to use the SB_SPI block.07:50
xobsIt has an initialization process, where 5 registers must be configured at boot.  Is there anything like that in litex?07:50
_florent_and just create a mux with the modified pads record in SpiFlash when bitbang is needed07:50
xobsSomething where, at reset, it steps through address/data pairs and writes them to registers, and continues when an "ACK" line is asserted.07:51
_florent_no sorry, i haven't used SB_SPI yet and not aware others project using it (with litex)07:51
xobsOkay, I'll just use a FSM to load the registers.  Thanks!07:52
xobs_florent_: do you have an example of indexing an array in the synthesized output? I have an array "init_dat = [0, 1, 0x80, 0x80, 12, 0xff]" and I'd like to access it from the design, but of course you can't index Python arrays with Signals.08:39
xobsI could create a Memory or similar, and manually manage it, but I feel like this must have a ready-made solution.08:39
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_florent_xobs: sorry was away10:21
_florent_you can use Migen's Arrays10:21
_florent_https://github.com/m-labs/migen/blob/master/examples/basic/arrays.py10:22
tpbTitle: migen/arrays.py at master · m-labs/migen · GitHub (at github.com)10:22
_florent_something like this: init_dat = Array(Signal(8, reset=dat) for dat in [0, 1, 0x80, 0x80, 12, 0xff]))10:23
xobsflorent: thanks! That looks like just what I need.11:55
xobsRight now it's much less elegant. For example: https://github.com/im-tomu/valentyusb/blob/master/valentyusb/usbcore/cpu/dummyusb.py#L3811:55
tpbTitle: valentyusb/dummyusb.py at master · im-tomu/valentyusb · GitHub (at github.com)11:55
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futarisIRCcloudhttps://abopen.com/news/openpitons-juxtapiton-processor-to-get-open-source-i486-core/21:11
tpbTitle: OpenPitons JuxtaPiton Processor to get Open-Source i486 Core - AB Open (at abopen.com)21:11
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