Tuesday, 2019-07-09

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CarlFK[email protected]:~/lhub/linux-on-litex-vexriscv$ ./sim.py00:24
CarlFKCompile board device tree...00:24
CarlFKsh: 1: dtc: not found00:24
futarisIRCcloudsudo apt-get install device-tree-compiler00:25
CarlFKfutarisIRCcloud: should I enter issues somewhere?00:38
futarisIRCcloudAsk _florent_ ...00:38
futarisIRCcloudMaybe we just need to update the README.md ...00:39
CarlFKrun_dut.sh: line 1: obj_dir/Vdut: No such file or directory00:40
CarlFKah.. bet we need build-essentials00:40
CarlFKmake[1]: g++: Command not found00:41
CarlFK[    0.449490] Unpacking initramfs...00:50
CarlFK[    3.730470] workingset: timestamp_bits=30 max_order=13 bucket_order=000:50
CarlFKthat was way more than 3 seconds :p00:50
CarlFKmount: mounting tmpfs on /dev/shm failed: Invalid argument00:52
CarlFKis that a problem?00:52
CarlFKbuildroot login: root - woot!00:53
CarlFKthe ascii art is all mangled00:53
CarlFK cat /proc/cpuinfo00:54
CarlFKprocessor: 000:54
CarlFKNo processor  :p00:54
CarlFKVivado wants to install to /tools/Xilinx - do I want that or /opt/Xilinx?01:15
futarisIRCcloudYou can install there, and symlink, or just install to /opt/Xilinx ...01:16
mithroCarlFK: please log bugs on the repo for now01:45
CarlFKmithro: k - looged the missing packages01:50
CarlFKmithro: is cpuinfo: processor: 0 a bug?01:50
CarlFKis arty what I want for:   ./make.py --board=arty --build02:05
futarisIRCcloudYes. If it's the board from linux.conf.au 2018.02:16
tpbTitle: GitHub - litex-hub/linux-on-litex-vexriscv: Linux on LiteX-VexRiscv (at github.com)02:22
CarlFK./make.py --board=arty --load02:22
CarlFKError: libusb_open() failed with LIBUSB_ERROR_ACCESS02:22
CarlFKshould I install the udev rules from https://github.com/litex-hub/litex-buildenv-udev ?02:23
tpbTitle: GitHub - litex-hub/litex-buildenv-udev: udev rules for LiteX BuildEnv supported boards (at github.com)02:23
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CarlFKExecuting booted program at 0xc100000003:04
CarlFK--============= Liftoff! ===============--03:04
CarlFKwhat should happen after that?03:04
CarlFKmithro: futarisIRCcloud.. I think it is stuck ^^^03:23
mithroCarlFK: That is when Linux should boot I think?03:23
mithroCarlFK: I'm guessing its probably the same issue that xobs ran into with csrs moving....03:24
futarisIRCcloudIt should boot. Someone has broken something.03:26
mithrofutarisIRCcloud: My guess is same change which cause an issue with https://github.com/enjoy-digital/litex/issues/21203:27
tpbTitle: Overlapped memory regions fail silently after bitstream generation · Issue #212 · enjoy-digital/litex · GitHub (at github.com)03:27
mithro> with the new offset of the csr region, which is at 0x02000000-0x12000000.03:27
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keesjI have had the same issue when flashing the stuff (on the arty board) but not when uploading via lxterm. In my case I am already on 0x2000_00005:56
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xobsAre there any examples of projects using SpiFlash()?08:50
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_florent_xobs: probably not published, let me prepare something09:08
xobs_florent_: I have something somewhat working, I think I just need to get the "dummy" value right.09:09
keesjI found (not migen based) this project quite interesting https://github.com/osresearch/spispy09:09
tpbTitle: GitHub - osresearch/spispy: An open source SPI flash emulator and monitor (at github.com)09:09
keesjwhere the spi interface is implemented in the FPGA09:09
_florent_xobs: ah sorry, i thought you were speaking of https://github.com/enjoy-digital/litex/blob/master/litex/soc/cores/spi_flash.py#L28409:16
tpbTitle: litex/spi_flash.py at master · enjoy-digital/litex · GitHub (at github.com)09:16
_florent_xobs: so if you are using SpiFlashDualQuad/SpiFlashSingle, yes you'll probably have to adjust the dummy parameter09:17
_florent_if you know the content of you Flash, you use mr command of the bios to figure it out09:18
_florent_see: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/15#issuecomment-49320334809:19
tpbTitle: Issue booting linux on ArtyA7 · Issue #15 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)09:19
_florent_keesj: indeed, that's interesting and probably tricky to be able to provide the read data in the amount of time allowed!09:20
xobsWhat is the "dummy" parameter units? It looks like it's the number of dummy clock cycles, minus a few cycles depending on the Wishbone width?09:21
_florent_it's in spi clock cycles, wbone_width is the length of the data transfer09:25
keesjof "course" with ddr we might have more time . I just expected the slave to be able to have more slack09:25
keesjI tried similar stuff (just tracing) on eMMC and that one starts at 12 Mhz does to 48 but then goes to 200 HS mode(200 Mhz , 8 data lines) that is really getting seriously challenging to emulate I guess09:27
keesjin their case they already know what blocks are going to be requested in what order09:28
_florent_not sure ddr would be a lot better since we the important thing here is latency09:28
_florent_if you know what is going to be requested, that' a bit easier indeed :)09:29
keesj(they presented a hack in the box amsterdam). pertty nice because for one of the guys it was really his first project09:30
keesjhttps://community.cypress.com/docs/DOC-9250  (there might be some way to configure the read latency)09:34
tpbTitle: Read Access Latency and Latency Code - KBA219110 | Cypress Developer Community (at community.cypress.com)09:34
keesjbut .. not if you are trying to attack secure boot09:35
_florent_mithro, futarisIRCcloud: just for info, the mem_map is not changed on linux-on-litex-vexriscv since we are forcing it10:41
_florent_just to be sure, i rebuilt everything for arty, it's working10:42
_florent_maybe the issue is related to a the spiflash and dummy bit configuration: https://github.com/litex-hub/linux-on-litex-vexriscv/issues/15#issuecomment-493203348.10:43
tpbTitle: Issue booting linux on ArtyA7 · Issue #15 · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)10:43
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daveshahsomlo: can confirm rocket works on TrellisBoard! https://www.irccloud.com/pastebin/kZ8dEAam/14:59
tpbTitle: Snippet | IRCCloud (at www.irccloud.com)14:59
daveshah(avoided the most recent patch that limited to 512MB, updated size in device tree and added free to BusyBox)15:02
_florent_daveshah: nice, thanks for the pull request on litex-boards,  i'll remove the 512MB limitation soon, main_ram was conflicting with csr on for linux-on-litex-vexriscv, haven't investigated yet15:17
daveshah_florent_: this was my hack a while ago https://github.com/daveshah1/linux-on-litex-vexriscv/commit/4bb8cd9a06565b34470dd5fc4b6b07a914dbcf56#diff-1c3a073ba4b12612a2c65941bd2a5842R6915:18
tpbTitle: Add TrellisBoard, 1GB hack · daveshah1/[email protected] · GitHub (at github.com)15:18
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daveshahbut before the changes on the litex side15:19
daveshahthat hack also needed a change to the vexriscv io range15:19
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_florent_thanks yes i'll change the location of the csr15:21
somlodaveshah: awesome!16:00
xobsIt seems like the magic dummy value I'm looking for is "6".16:03
somloI have an "action item" to update to the latest busybox, I should remember to also add "free" to the list of utilities :)16:03
xobsNow I just need to figure out why SPI writing isn't functioning correctly.  Reading works, erasing works, reading the SPI ID works, but no data actually gets written.  I'm wondering if it isn't misaligning the number of clock pulses somehow...16:04
daveshahsomlo: It would be nice to try a NFS rootfs at some point (I did this to test a bigger buildroot system with the vexriscv stuff)16:06
daveshahProbably no good for a distro without a faster Ethernet core though...16:07
somloalso, with the way Rocket's external connectivity is wired, it'd be nice to have the AXI port speaking directly to DRAM separated from the CSR/MMIO + bootrom + device buffers wishbone bridge, which whould be connected to the MMIO AXI port on Rocket16:10
somlodaveshah: I still haven't had a chance to try ecp5versa placement hacks (now that I showed my bosses it boots, my reward is that I get to write a crap ton of reports :D16:14
somlobut what I meant to ask was, did you get the ethernet working on ecp5versa? Even when I leave out the MMU and fit within 45K slices comfortably, it still won;t link up for me16:15
daveshahYes, but you have to use a system clock frequency ≥60MHz16:18
daveshahand accept that timing marginally fails16:18
daveshahTFTP didn't work for me at 50MHz, not sure why16:18
somlooh, that explains it16:18
daveshahI think the LiteX TFTP client could do with some reliability improvements16:18
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CarlFKLiftoff still doesn't liftoff22:09
daveshahHave you tried serial boot?22:10
CarlFKthat is all I have tried22:11
daveshahWhat about the simulator?22:12
CarlFKthat worked yesterday22:12
daveshahMight as well double check today22:12
CarlFKI'll try now, yeah..22:12
daveshahThat should at least confirm your emulator and kernel are built correctly22:12
CarlFKits booting22:14
daveshahWhat board is this?22:16
CarlFKArty  http://paste.ubuntu.com/p/qJKDXZt8XB/22:17
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)22:17
daveshahHmm, not sure what's going on22:25

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