Monday, 2019-07-08

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xobsAre there any examples of using the built-in litex SpiFlashDualQuad with write support and/or raw SPI commands?02:18
xobsI see, spiflash.c contains code to do that, if you set with_bitbang=True02:42
futarisIRCcloudJust noticed that some boards have moved, e.g. ac701.py :02:46
futarisIRCcloudhttps://github.com/litex-hub/litex-boards/blob/master/litex_boards/community/targets/ac701.py02:46
tpbTitle: litex-boards/ac701.py at master · litex-hub/litex-boards · GitHub (at github.com)02:46
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_florent_xobs: i just saw https://github.com/im-tomu/foboot/issues/12#issuecomment-50912305708:37
tpbTitle: Replace PicoSoC XIP flash controller with LiteX version · Issue #12 · im-tomu/foboot · GitHub (at github.com)08:37
xobs_florent_: I'm trying to figure out what's different.08:37
xobsOne thing I've just discovered is that SRAM and the CSRs appears to have moved.08:38
_florent_xobs: anything i can do to help? can you give me the configuration you are using or give me a link to your SoC?08:38
xobsNow CSRs overlap with my SRAM region, which might be causing some problems.08:38
_florent_xobs: ah indeed08:38
_florent_xobs: you can still use the old mem_map if it's easier for now08:38
_florent_xobs: you just need to force it on your SoC08:39
_florent_xobs: if you give me a link to your SoC, i'll tell you what needs to be done08:39
xobsI just moved my SRAM to 0x01000000 and now it's working again.08:40
xobsSo the issue was that there was an overlap in the "csr" region and my "sram" region, which was causing RAM to silently not be accessible.08:40
_florent_ok good, interesting, i would need to investigate08:41
_florent_would you mind creating an issue with for that?08:42
xobsSure thing!08:42
_florent_for info, here are the mem_map changes: https://github.com/enjoy-digital/litex/commit/9d170b09442f1f5947b7a024639339397bcab6b008:43
tpbTitle: soc_core: rearrange default mem_map · enjoy-digital/[email protected] · GitHub (at github.com)08:43
_florent_we no longer have the 256MB limitation, so the idea was to free up the space after main_ram for boards that have > 512MB of memory08:44
_florent_but that's only a default mem_map and you can still use a custom mem_map when needed08:45
_florent_here is how we can force the mem_map: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L2508:46
tpbTitle: linux-on-litex-vexriscv/soc_linux.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)08:46
xobsI noticed that when I went through "git log" trying to figure out what changed to break my design.  I think I have it working now!08:48
_florent_ok good, thanks for the issue, a check is probably missing, i'll fix that08:51
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somlowant a *64-bit* RISC-V free-as-in-freedom computer that can run upstream Linux? check out http://www.contrib.andrew.cmu.edu/~somlo/BTCP/12:48
tpbTitle: A Trustworthy Free/Libre Linux Capable 64bit RISC-V Computer (at www.contrib.andrew.cmu.edu)12:48
_florent_somlo: thanks13:13
keesjI am thinking of running my home server on the arty13:17
keesjI do think I want to rely on debian for the base system13:19
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keesjhttps://wiki.debian.org/RISC-V13:19
tpbTitle: RISC-V - Debian Wiki (at wiki.debian.org)13:19
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somlo_florent_: thanks for the csr alignment patch, 64bit test in progress. Might have a small fix-up PR, once I'm done testing :)14:15
somlo_florent_: https://github.com/enjoy-digital/litex/pull/21414:58
tpbTitle: soc_core: additional csr_alignment follow-up fixes by gsomlo · Pull Request #214 · enjoy-digital/litex · GitHub (at github.com)14:58
somlo_florent_: I also ran a "grep -r '4\*' --include=*.py" in the litex repo top-level directory and got a bunch of "addr + 4*i" results in e.g. litex/tools/litex_client.py, comm_usb.py, etc. -- not sure if any of that has anything to do with CSR alignment, but it's not part of the follow-up PR #214 (which gets things working for me in sim and on the nexys4ddr)15:01
daveshahsomlo: can you send me a prebuilt boot image for the rocket linux?15:29
daveshahI think I have it fitting on a Versa ECP5 now with highly experimental (possibly broken) DSP inference and a reduced threshold for picking BRAM over DRAM (this causes the ethernet domain to fail timing, but I'm turning a blind eye to that) along with the old -abc9 -widelut16:02
daveshahBut I'm on a bad internet connection and don't have a suitable 64-bit RISC-V toolchain set up so can't actually see if it goes into Linux yet16:03
daveshahAnnoyed that the Arch-provided riscv64 gcc only seems to have lp64d abi support16:04
daveshah\o/ got as far as Kernel panic - not syncing: incorrect cpio method used: use -H newc option16:24
daveshah\o/ it works, after adding -H newc16:28
daveshahsomlo: if you want to try this, use Yosys from https://github.com/daveshah1/yosys/tree/ecp5_rocket_versa5g and `synth_ecp5 -abc9 -nowidelut -dsp`16:28
tpbTitle: GitHub - daveshah1/yosys at ecp5_rocket_versa5g (at github.com)16:28
daveshahYou'll have to ignore the timing failure in the ethernet domain for now, but it seems to be inconsequential16:29
flammitxobs: thanks for the tip on the spiflash.c/bitbang!  it's exactly what i was trying to accomplish (though from linux userspace)16:45
daveshahHmm, looks like *lowering* the system clock frequency from 75MHz to 50MHz so it passes timing causes TFTP boot to fail16:55
daveshahbut it works reliably enough at the overclocked 75MHz16:55
sorearis the *MII clock somehow being generated from the 75mhz?17:09
daveshahNope17:09
daveshahTotally different domain17:09
daveshahseems fine at 60MHz too17:09
somlodaveshah: http://mirror.ini.cmu.edu/boot.bin (sorry for the delay, had to step out of the office for a few hours)18:26
somlodaveshah: wait a sec, that one's broken, uploading a working one :)18:26
daveshahno problem, I managed to build one in the end anyway18:27
somlooh, ok18:27
daveshahForced me to set up the toolchain18:27
daveshahWill be useful in the future anywau18:27
daveshahYour instructions seem good other than the cpio issue above18:28
daveshahPerhaps a difference in the cpio arch linux bundles18:28
somlodaveshah: catching up with the accumulated IRC conversation :)18:28
somlodaveshah: I'm rebasing to the freshest 5.2 kernel and _florent_'s latest LiteX, then I'll try the ecp5versa hack -- thanks!18:46
somloI'd be curious if this works on the TrellisBoard, btw :)18:46
somlodaveshah: on Fedora 30, `man cpio` contains ``-c  Identical to "-H newc", use the new svr4 portable format ...``18:50
somloso I was *trying* to do the right thing, not sure if "-c" is a Fedora-only hack?18:51
daveshahYup, need to sort out the TrellisBoard setup in LiteX with the new memory map stuff then I can test that18:51
daveshahArch Linux `man cpio` says `-c     Use the old portable (ASCII) archive format.  This is  the  same as -H odc.`18:53
somlooy18:54
daveshahMight be an older version, copyright is 201518:54
somlothe exact opposite :(18:54
daveshahNo, looks like it is the latest upstream18:54
daveshahHmm18:54
somlook, maybe I'll just spell it out explicitly, then :)18:54
daveshahSeems like arch linux is upstream cpio18:55
daveshahSeems the safest option18:55
somlodaveshah: done, good thing I was retracing all my steps anyway, now I get to test it to make 100% sure my instructions still work for me :)18:57
somloand thanks for catching the discrepancy!18:57
daveshahLooks like https://src.fedoraproject.org/rpms/cpio/blob/master/f/cpio-2.9-rh.patch is the cause18:58
tpbTitle: Tree - rpms/cpio - src.fedoraproject.org (at src.fedoraproject.org)18:58
somlohmmm, not very nice of them...19:01
somloI mean, unless they're valiantly trying to push that upstream... :)19:02
somlonope, the patch isn't showing up anywhere on https://savannah.gnu.org/projects/cpio/ so unless I've missed something, RH just went ahead and swapped the meaning of "-c" in cpio...19:07
tpbTitle: GNU cpio - Summary [Savannah] (at savannah.gnu.org)19:07
mithroflammit / xobs: An older version of the spi_flash module is in litex-buildenv -> https://github.com/timvideos/litex-buildenv/blob/master/gateware/spi_flash.py19:36
tpbTitle: litex-buildenv/spi_flash.py at master · timvideos/litex-buildenv · GitHub (at github.com)19:37
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futarisIRCcloudsomlo: Looks good.23:40

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