Tuesday, 2019-07-02

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daveshahsomlo: seems the problem is between c907899 and the yosys 0.9 rc (so not from the abc9 PR). I'm bisecting it now11:19
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somlodaveshah: just noticed you said you were bisecting -- missed this when I got into the office earlier this morning :) Thanks again for the fix15:05
* somlo goes to work on updating to the new LiteX memory map...15:05
_florent_somlo: if you want to keep the old memory map for you SoC, you can still force it to the old memory map by doing something similar to this: https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py#L25-L3316:02
tpbTitle: linux-on-litex-vexriscv/soc_linux.py at master · litex-hub/linux-on-litex-vexriscv · GitHub (at github.com)16:02
somlo_florent_: it looks like main ram is still at 0x4000_0000, and all I need to do for the rest is update the DTS blob I'm compiling into BBL17:03
somloso I think I'll be OK for now...17:04
somlohowever (and feel free to ignore me, just thinking out loud here) -- I'm wondering how much of a disruption, and how difficult it would be to *swap* the MMIO/CSR/etc. and main-ram around the 0x8000_0000 boundary -- have uncached accesses below that address, and cached above17:05
somlobased on the intuition that main-ram might grow bigger, faster than the need for MMIO/CSR register space17:06
_florent_somlo: yes i also want to see if we can improve that17:45
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