Wednesday, 2019-06-26

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somlofutarisIRCcloud: I had considered asciinema, but it would be a PITA to serve a self-sufficient "video" with no external dependencies, from a web server I don't control...01:28
futarisIRCcloudI've used it to record to a local file, and just run that through asciicasttogif for a smaller file...01:29
somloI do like that it's just recording the ascii sequence -- probably orders of magnitude less "bloat" :)01:29
somlowhat, make an animated gif? I guess that would pass the "self-sufficient" criterion :)01:29
futarisIRCcloudYep. for a example.01:31
somloright now it's "fire up simplescreenrecorder; select a rectangle or window; hit record, get an mp4 video"01:31
somlobut I'll have to look into the animated gif thing, it does sound much cooler on the face of it :)01:32
futarisIRCcloudA ~1 minute text video ended up being a 1.6 MB GIF.01:32
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keesj_there is also typescript back from the ... 70's ( type script ) control -d to stop and then "cat typescript ; while read i ; do echo $i ; sleep 1 ; done" or perhaps even
tpbTitle: Bash script to convert typescript to gif Origin from · GitHub (at
keesj_normally use obs now. add a camera that points to the board, once for my nice face and audio for .. audio11:04
keesj_else also a tool called recordmydesktop11:04
keesj_telnet towel.blinkenlights.nl11:07
keesj_hm it currently ain't working for me11:07
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felix_what is the best way to have the data size of a stream element that is used in one core to have a size that isn't fixed, but depends on a build-time instantiation parameter of that core? the problem i'm trying to solve is that depending on the video format the link between the photonsdi core and the gtp transceivers has a different lenght; the width and configuration of the scrambler also depends on this15:11
_florent_felix_: i'm generally just using a data_width parameter for that, ex:
tpbTitle: litesata/ at master · enjoy-digital/litesata · GitHub (at
_florent_this way is similar to parameters in VHDL/Verilog18:03
_florent_another way is also to pass the lower level modules to higher level modules and deduce higher level parameters from lower level modules18:04
somloI just noticed libbase/spiflash.c -- addresses there are still "unsigned int", and should probably be "unsigned long" instead...18:10
somloprobably missed a bunch of places I'm not directly using with Rocket (yet)...18:11
_florent_somlo: thanks, i'll check that18:15
felix__florent_: ah, answered my question. thx :)18:40
tpbTitle: litesata/ at db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 · enjoy-digital/litesata · GitHub (at
tpbTitle: litesata/ at db5d2f7881161ce5b9a10a0ab42555f884b9d7c1 · enjoy-digital/litesata · GitHub (at
_florent_felix_: ok good, also just for info, i'm trying to have generic transceivers wrappers here:
tpbTitle: liteiclink/liteiclink/transceiver at master · enjoy-digital/liteiclink · GitHub (at
_florent_the aim is to be able to be flexible enough to be reused by cores requiring transceivers18:52
felix_sounds good; will have a look when i've finished the higher levels of photonsdi18:53
somloneed to figure out what the deal is with BBL's alleged ability to trap and emulate floating-point instructions -- busybox (init) was faulting because it *thought* it's runningon rv64imafdc, and was trying to access FP registers20:27
somloonce I got it to compile as rv64imac (no "fd"), it started working20:27
_florent_somlo: great, congrats20:48
somloLiteX is the best! :)20:50
_florent_how much resources is your Rocket SoC using on the nexys4ddr?20:55
somlo_florent_: 15406 total LUTs, of which 12802 for the RocketChip (with mmu, no fpu) -- according to top_utilization_hierarchical.rpt22:46
somloI also built it for an imaginary ecp5versa (with an 85k fpga), and utilization was somewhere in the 66%22:47
somlodaveshah: ^^ (also, I'd be curious if this could work on a trellis board)22:48
daveshahYup, I'll have a play22:49
daveshahIncidentally, might be worth trying this PR and synth_ecp5 -abc922:49
tpbTitle: write_verilog: inline internal cells that are used exactly once by whitequark · Pull Request #726 · YosysHQ/yosys · GitHub (at
daveshahI was seeing a 25-30% area reduction for a basic Rocket config22:50
daveshahMight just squeeze it into a Versa22:50
somlocool, I was gearing up to refreshing my local yosys RPM package, I'll give it a spin tomorrow22:50
daveshahSorry, pasted the wrong PR22:52
daveshahI meant this one
tpbTitle: Pull Requests · YosysHQ/yosys · GitHub (at
daveshahGah, has github mobile changed what it copies22:52
tpbTitle: WIP "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs) by eddiehung · Pull Request #1098 · YosysHQ/yosys · GitHub (at
daveshahThat's the one22:52
somlogot it, thanks!22:53
daveshahThe plan is to merge this into master soon after the Yosys 0.9 release (which should be in the next few weeks)22:55
daveshahSo that there is some kind of stable reference point before a big breaking change22:55
somlooh, nice, an official yosys release -- might be what it takes to get the Fedora maintainer to refresh the official rpm :)22:56
sorearHas there been any work or discussion about FPGA optimized 64 bit cores (vex based or otherwise)?22:58
somloI'll definitely take it for a spin first thing tomorrow morning22:58
somlosorear: not sure about discussion, but as far as rv64* (and as far as I'm aware of), there's Rocket, and there's Ariane23:47
somlothen, if you want an actual full-featured linux distro like Fedora, you'd need support for (at least emulation of) F and D23:50
somlowhich I am in the process of wrapping my head around, from a practical standpoint (I get how it ought to work in theory :) )23:50
sorearbefore the unleashed boards were generally available a couple people were using xilinx dev boards for software work23:53
sorearthe xilinx tools and the rocket FPU interact badly and while it fit, timing was dramatically better with the FPU removed23:53
sorearso I've seen bbl fpu emulation in actual use23:53
somloIIRC, the original sifive unleashed thing was on a virtex 723:53
somlobefore they made an ASIC23:54
sorearthat was UCB's go-to board before sifive even existed so23:54
somlobut even an artix7 (nexys4ddr) can fit a single FPU-enabled core; I just happen to have a non-negotiable requirement to use F/OSS tools only, which means ECP5, which may or may not end up having enough room for a FPU-enabled core; right now it doesn't, and I'm working on the assumption I'll have to use emulation regardless23:56
sorearwell the Rocket FPU is one or two 53x53 multipliers23:56
sorearwhich are going to be hell until DSP inference works23:56
daveshahIs it the Rocket FPU that basically shoves a load of registers after the whole thing and relies on retiming?23:58
daveshahThat's going to be fun to fix even with DSP inference23:58

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