Monday, 2019-06-24

*** tpb has joined #litex00:00
*** tweakoz has joined #litex03:13
*** rohitksingh_work has joined #litex05:14
_florent_Dolu: nice for the ATWILC1000, not sure we are currently a lot faster with the onboard ethernet PHYs :)05:43
*** sorear_ has joined #litex06:16
*** sorear has quit IRC06:24
*** Dolu has quit IRC06:28
*** Dolu has joined #litex06:29
*** sorear_ is now known as sorear06:29
*** tweakoz has quit IRC08:10
keesj_is there a nice way to combine the wishbone uart interface and the serial?08:17
keesj_like.. makeking litex_term read/.write an in memory buffer (over the wishbone uart interface)08:18
*** rohitksingh_work has quit IRC09:59
*** rohitksingh_work has joined #litex10:01
*** Dolu1990 has joined #litex10:03
*** rohitksingh_work has quit IRC10:44
*** rohitksingh_work has joined #litex10:45
*** Dolu1990 has quit IRC11:13
_florent_keesj_: you can use the UART wishbone bridge for that12:08
_florent_keesj_: since it gives you access to the wishbone, if you attach a memory to the wishbone, you'll be able to access it over UART12:09
keesj_but.. I want to combine it witha core with also uses the uart12:26
keesj_Also I am playing with the AutoCSR at the moment and would like to read out a signal (32 bits wide). Should I be able to assing the storage to the signal in a sync block?12:29
keesj_or perhaps even = self.read_counter ?12:29
*** rohitksingh_work has quit IRC13:19
_florent_keesj_: with the bios, you can write or read memory with mw/mr command13:41
_florent_so you could add a script on top of litex_term to do that, but that will be a bit slow13:41
_florent_for the csr, you can do, self.sync +=
_florent_you can assign CSR signals as you would do for others signals13:43
keesj_RROR: [Synth 8-2576] procedural assignment to a non-register readc_storage is not permitted [/home/why/projects/ddr3/litex/exset/10_trace_ddr_state/build/top.v:1435]13:49
keesj_(using CSRStorage and Signal)
tpbTitle: class DDRStateCounter(Module,AutoCSR): def __init__(self,ddrstate4): - (at
keesj_wire [31:0] readc_storage;14:31
keesj_e.g. readc_storage is defined as a wire not a register14:31
keesj_in most examples I see the logic is kinda reversed e.g. CSR storage is assigned to a different signal (and CSRSatus has a status that I can probably write to)14:35
_florent_keesj_: ah yes sorry, you should use a CSRStatus for that no?17:35
keesj_CSRStatus indeed worked. still from the documentation it looks like CSRStorage is a read / write register17:50
*** flammit has joined #litex18:13
_florent_you can read a CSRStorage, it will return the value that was written to it. You can also use write_from_dev on a CSRStorage, but it's only needed on very specific cases, otherwise, i would recommend splitting in CSRStorage/CSRStatus19:32

Generated by 2.13.1 by Marius Gedminas - find it at!