Monday, 2019-06-17

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keesj_florent__: I was giving the sdcard changes a spin on the master branch . the output is .. different from what the code I submitted e.g. http://paste.ubuntu.com/p/8jhRMvFFTc/ vs. the ourput here https://github.com/enjoy-digital/litesdcard/pull/308:34
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)08:34
keesjI tried (and built) a checkout of version https://github.com/enjoy-digital/litesdcard/commit/6b3dbef45a6603f77fd4944e9ddbd7d78a1ed13c (e.g. mostly my changes" but the output here is also the same.08:35
tpbTitle: Link against ctr0-$(CPU)-ctr.o v.s. ctr0-$(CPU).o · enjoy-digital/[email protected] · GitHub (at github.com)08:35
keesjI will (later this week) try to understand what is going on(if my setup changed or that the other commits caused a problem08:36
_florent__keesj: i integrated your pull request + the one from bunnie09:32
_florent__keesj: from what i see, the difference is on the error count in multiple blocks mode?09:33
keesjin the pastebin line 9 has the first error (crc) but then still the cid is being read09:49
keesjhttp://paste.ubuntu.com/p/8jhRMvFFTc/ lines 909:49
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)09:49
keesjhmm perhaps this is just the chip startup ..09:50
keesjand my setup is not very professional https://i.imgur.com/hlyKF3e.jpg09:53
_florent__keesj: yes i can be the startup of the a bad SDCard state09:59
_florent__i/it10:07
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keesjwhere can I lookup the io pin and bank mapping (for the fpga on the arty) ?14:35
keesjlitex/migen does this set_property INTERNAL_VREF 0.675 [get_iobanks 34] and think I need something similar for my io connected to the pmod-c (high speed)14:38
_florent__keesj: sorry, i'm not sure to understand the question14:41
_florent__keesj: you can add io extension like this: https://github.com/enjoy-digital/litesdcard/blob/master/examples/arty.py#L3214:42
tpbTitle: litesdcard/arty.py at master · enjoy-digital/litesdcard · GitHub (at github.com)14:42
_florent__https://github.com/enjoy-digital/litesdcard/blob/master/examples/arty.py#L8714:42
tpbTitle: litesdcard/arty.py at master · enjoy-digital/litesdcard · GitHub (at github.com)14:42
keesjthe problem (I think I am having) is that I am using SSTL15 as IO standard. I either need to provide an external voltage reference or set the value (as is done for  io bank 34)14:50
keesjthis magic line https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/arty.py#L25514:51
tpbTitle: litex/arty.py at master · enjoy-digital/litex · GitHub (at github.com)14:52
keesjhence I need to know on what IO bank the BGA pin D15 is for example14:53
_florent__ah ok14:56
_florent__https://www.xilinx.com/support/packagefiles/a7packages/xc7a35tcsg324pkg.txt14:56
_florent__https://www.xilinx.com/support/package-pinout-files/artix-7-pkgs.html14:56
tpbTitle: Artix-7 FPGA Package Device Pinout Files (at www.xilinx.com)14:56
keesjcool! thanks15:09
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*** _florent__ changes topic to "LiteX Soc builder and Cores (http://enjoy-digital.fr) / Github : https://github.com/enjoy-digital, https://github.com/litex-hub / Logs: https://logs.timvideos.us/%23litex/latest.log.html"19:15
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sorearoh, no +t21:18
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felix_what is the difference between payload and param in litex streams? in some part of litevideo payload gets used for things i'd expect param to be used (the output timing parameters that get passed from csr regs to the timing generator) and in another place it's the other way around (the video_out_layout where hsync and vsync are uses as param). also is there some more documentation than the code and the22:15
felix_notes and tips in the litex-buildenvironment repo wiki?22:15

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