Monday, 2019-06-10

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ambro718I have two questions about the RX stream for LiteEthMACCore.18:59
ambro7181) Is last=1 guaranteed to be seen after first=1 or is it possible to see another first=1 without last=1 just before it?18:59
ambro7182) What exactly does error mean?19:00
_florent__hi ambro71819:35
ambro718I think I'm making good progress with the Ethernet DMA :)19:36
_florent__for 1), first is not use in LiteEth, only last19:36
ambro718For error in RX stream I think I am responsible to detect any error and mark the packet as bad so it won't be given to the network stack in the OS.19:37
_florent__for 2) error is set to 1 if an error is detected in RX, IIRC it's mainly used for the CRC error19:37
_florent__yes, that's the idea19:38
ambro718Does liteeth check the length of received packets?19:38
ambro718Could it give huge packets in RX stream?19:38
_florent__yes we check the length:
tpbTitle: liteeth/ at master · enjoy-digital/liteeth · GitHub (at
ambro718Great, than I won't worry about that.19:41
ambro718Also about error, I see its width is dw/8, is it correct to check just if it's not zero?19:42
_florent__but if you are replacing with a DMA, you'll have to handle it :)19:42
ambro718Ah yes I see now you pointed to the SRAM code.19:42
_florent__yes there is an error if != 019:44
ambro718_florent__: If you want you can check out the current code. Common and TX code is mostly written, but I never tried to compile it.
tpbTitle: liteeth/ at dma · ambrop72/liteeth · GitHub (at
ambro718I'd appreciate any hints or criticism :)19:50
ambro718Will this work:  a.eq(b[0:14]) ?20:19
_florent__ambro718: thanks, i'll look a that tomorrow21:04
ambro718Great, if you can!21:04
ambro718I think I'll need to add the FIFOs manually though, they don't seem to be part of LiteEthMACCore, and seems to add them manually21:08
DolufutarisIRCcloud  sirq is as far i know, Software IRQ21:38
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