Wednesday, 2019-06-05

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Dolu updated with the fix the WFI freeze09:41
tpbTitle: GitHub - enjoy-digital/VexRiscv-verilog: Using VexRiscv without installing Scala (at
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ambro718Will this do the expected thing?  comb += sig.eq(default); comb+= If(condition, sig.eq(something)); ?18:56
_florent__ambro718: yes it will be fine19:03
ambro718Ok thanks.19:03
ambro718Is is a problem to have two sync drivers of a signal that may both execute and set it to the same value (set a single bit to 1)?19:29
_florent__no, the last assignment will win19:31
ambro718Makes sense, thanks.19:31
ambro718I think it would be nice if sync/comb weren't separate but it would be like in FSM, you'd use different ways to sync-assign and comb.assign. Like .eq() for comb-assign and .next() for sync-assign.19:36
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