Sunday, 2019-05-26

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key2what do you guys think about that: i generate a ROM for my usb HS core using kconfig
tpbTitle: untitled - asciinema (at
keesjI think it is kinda interesting. do you parse the .config afterward in your python code?15:40
keesjI like that litex is mostly python but having done kconfig type stuff before I also see some potential. was it much work compared to creating a python structure?15:41
_florent__key2: thanks for sharing, that's nice. Being able to configure the cores with kconfig could also be useful to ease custom cores generation/integration when used with OSes.17:40
key2well in this case, I generate a config.h17:41
key2which then gets compiled and generate the ROM17:41
key2as well as generates a python file for migen17:41
key2I guess I should have shown the process more deeply17:41
_florent__feel free to share more :)17:41
key2well once compiled it generates a file like this17:53
tpbTitle: Snippet | IRCCloud (at
key2which is used by the EP0 controller in order to answer the request the host send17:54
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ambro718Hi. I'm interested in this line that controls the memory clock rate:
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
ambro718This defines the ratio between sys_clk_freq and the memory frequency, or data rate?18:28
ambro718so if sys_clk_freq is 100 MHz, is the memory clock frequency 400 MHz or 200 MHz?18:28
ambro718My experience with Vivado is that 1:4 means the frequency of the logic clock (sys_clk_freq) is 1/4 the frequency of the memory clock.18:30
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_florent__ambro718: your understanding is correct. This ratio has to be defined for the SDRAM module (to compute correct timings), but also for the PHY:20:23
tpbTitle: litedram/ at master · enjoy-digital/litedram · GitHub (at
_florent__But S7DDRPHY currently only supports DDR3 with 1:4 ratio, DDR2 with 1:2 ratio20:24
ambro718_florent__: so with this Arty code, with 100 MHz sys_clk_freq, we get 400 MHz clock period for the clop and 800 MHz per-pin data rate?20:24
ambro718* for the chip20:25
_florent__yes that's correct20:26
ambro718_florent__: Well then I see two problems. First is that we are running the RAM too fast for the Arty board.
tpbTitle: Arty A7 Reference Manual [Reference.Digilentinc] (at
ambro718Max. clock period   3000ps (667Mbps data rate)20:27
ambro718_florent__: second is that the ck_to_cycles is written like the ratio was the ratio between the system clock and ram clock frequency, when CK actually means one clock edge.
tpbTitle: litedram/ at master · enjoy-digital/litedram · GitHub (at
ambro718My understanding is that CK in data sheets means one clock edge (half clock period), so with 1:4 ratio we need to multiply by 8 to get from CK to system clocks.20:31
ambro718Here's the data sheet for the RAM chip on my Arty board (which is actually a different chip than the reference says):
ambro718Somewhere this is hidden: "Unit “nCK” represents one clock cycle of the input clock, counting the actual clock edges".20:34
ambro718and the nCK values of the timings are in the right order of magnitude (I believe nCK here is what CK is supposed to mean in this code)20:35
ambro718Am I making any sense?20:42
_florent__ambro718: i'm not able to look at that now, but will do tomorrow, i'll answer here is you are still connected20:54
ambro718Ok great, thanks, I'll come come back here tomorror at around the same time.20:54
ambro718Huh, maybe nCK does actually mean a full clock cycle. It's hard to find it explained in a clear way.21:06
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