Thursday, 2019-05-23

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sb0_florent__: do you have a ZC706?06:03
_florent__sb0: no i don't have this one07:06
keesj_florent__: I am reading your comment to use a converter (to convert my 4 bits serdes signal to a serial stream) but I remain clueless. I think that what I need to do is to "speed" up the scope to provide 4 samples per cycle then I can match my serdes inputs to the samples07:20
tpbTitle: Ubuntu Pastebin (at
keesjpossibly the SubSampler has something to do with it07:24
_florent__keesj: from what i remember, you want to concatenate the data outputed by the ISERDESE2 to form a stream with a larger data-width?07:24
keesjI want to represent my serial stream as serial stream07:26
keesjfrom 1 bit input -> 4 bits serdes -> 1 bit output for the logic analyzer07:27
keesjI think I need to modify around here
tpbTitle: litescope/ at master · enjoy-digital/litescope · GitHub (at
keesjthe storage should create 4 "samples" v.s. the 4 bits sample07:29
_florent__keesj: but here we are using  serdes because the frequency is too high for the FPGA fabric, so that's not possible to have your data as a 1-bit data stream in the FPGA fabric07:29
_florent__keesj: if you want to do a modification, you'll need to do it in the software07:30
keesjI kinda know that ( and I am fine for the "real" world to be like this) but I still should be able to view this data using litescope as if it was serial07:31
keesjon the host side you mean?07:32
_florent__yes on the host07:32
_florent__maybe use the capability to export the dump in python, then do the adaptation on this and reimport the modified dump, then export to a vcd with litescope software07:34
keesjI do not sea a reason why this would not work e.g. instead of a 1 bit clock domain create a 4 bit clock .. somewhere around here
tpbTitle: litescope/ at master · enjoy-digital/litescope · GitHub (at
keesjof course (indeed) I can do it in software07:37
keesj2 bit clock (not 4)07:38
_florent__i'm not sure to understand what you want to change in the gateware07:39
_florent__if you do a 1-bit serial stream in the gateware, the frequency will be too high, so you need to stay with the 4-bit serial stream in the gateware07:39
keesjI Want to store the 4 bits I get every clock cycle to separate sample memory locations. I don't need the 1 bit stream indeed just to store it in the buffer like that07:44
keesjevery clock cycle store bit[0] of the serdes to memory location[0] ,, bit one to location[1] etc also advance the "scope" of 4 samples07:46
keesjI think I understand better know what I want. I will try making an example07:51
_florent__thanks, an example will help me understand what you want to achieve07:56
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