Tuesday, 2019-05-21

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keesjI have an error I do not quite understand https://paste.ubuntu.com/p/DYwxpZDThk/08:52
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)08:52
keesjafter (way to long) i discovered my signal are not sstl135 but 1.8v (hence I was not seeing the low values....08:53
keesjNow I am trying to use SSTL18  (I II I_DCI II_DCI) to see where it goes but somehow xilinx thinks differently about what I am asking08:53
keesjspecifying SSTL18_I does "fix" the problem in terms of warning.08:56
keesjrubber ducking herer .. but the reason is that not all IO standards are available on all ports (SelectIO give better information on this as there is a table with the compatible ports)09:06
keesjsoo. doing a typo in the IOSTANDARD fails to late09:07
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_florent__keesj: yes, this kind of errors are reported late in the build...11:27
keesjI lowered the ddr speed (to 400 MHz) improved the grounding11:42
keesjthe signals remain high but when I ground them still they remain high about 1/2 of the time11:43
keesjyestedey it looked like this https://i.imgur.com/OWmh0Nz.png11:43
keesjwhen I ground it looks like https://i.imgur.com/luJTech.png (the two upper lines)11:45
keesjare "grounded" but is still looks like $RANDOM stuff horrible11:46
keesjnow it looks like https://i.imgur.com/CCCWKxj.png11:47
keesj(this is clocks + nwe) the clock look crap but at least the voltage on the NWE is low enough11:48
keesjlet me make a niver measurement11:49
somlois there some way (in LiteX, or the underlying migen) to have $display statements added to the generated verilog code matching some specific place in the Python (e.g., in a FSM)?13:38
_florent__yes, you can use use Display13:41
somlois that a migen thing, then? Only two instances in the litex code base, none of them something I can immitate :)13:42
somlo^ looking for an example of how to use it, or where to RTFM on the syntax13:45
somlohmm, I see there's a few examples in litesdcard/sim/sim.py13:51
_florent__somlo it's very similar to printf14:02
somlo_florent__: thanks, makes sense :) the litesdcard examples only show hardcoded strings, but I can imagine if it's getting translated into verilog $display it can probably accept %h and %b and friends as well...14:03
_florent__you can use it like that: https://github.com/enjoy-digital/linux-on-litex-vexriscv/commit/02a8b74e839eb8b72486a43d529dce20b1e43cbd14:03
tpbTitle: sim: add debug traces on periphs accesses · enjoy-digital/[email protected] · GitHub (at github.com)14:03
somlothanks, looks reasonable and straightforward :)14:05
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somloapparently, Display(...) doesn't work from inside an fsm.act(...)17:17
somlo... unless I'm doing something subtly wrong...17:17
_florent__ah yes, possible17:18
_florent__you can workaround it with:17:19
_florent__display = Signal()17:19
_florent__set display.eq(1) inside the FSM17:19
_florent__(where you want to display things)17:19
_florent__then add a self.sync += If(display, Display("..."))17:19
somloand then write a self.sync where I display e.g. fsm.decoding[fsm.state] and the like17:20
somlook, trying that now17:20
somloI'd also have figure out when to set display.eq(0) or else it'll just stay set, right?17:22
somloassuming it gets implemented as a register/flipflop17:23
somloor, maybe I need to understand and use NextValue(display, X), to get it set only when appropriate...17:26
_florent__you just need to set display.eq(1), it will automatically be 0 (reset value) in the others cases17:30
somlothat should make it easier, then -- thanks! :)17:30

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