Thursday, 2019-05-16

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somlo_florent__: trying to generate a dram controller with exposed CSR bus, and I'm wondering what I screwed up (https://github.com/gsomlo/litedram/tree/gls-expose-csr)11:21
tpbTitle: GitHub - gsomlo/litedram at gls-expose-csr (at github.com)11:21
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somlooh, when cpu_type="None" there are no wishbone masters, so the entire block where CSR regions are generated and connected to the bus is skipped in SoCCore's do_finalize :)13:04
somlo_florent__: I'll try to cook up a patch that executes some part of this block (https://github.com/enjoy-digital/litex/blob/master/litex/soc/integration/soc_core.py#L483) if self.csr_expose is true, regardles of whether there are any self._wb_masters :)13:15
tpbTitle: litex/soc_core.py at master · enjoy-digital/litex · GitHub (at github.com)13:15
_florent__somlo: i was just looking at it13:16
_florent__somlo: i'm doing the changes13:17
somlook, cool, thanks!13:17
somlolike, self.csr will be the only master on the csr_bus.Interconnect, or something13:18
_florent__somlo: https://github.com/enjoy-digital/litex/commit/526ba1b165a09f6c0b51646a4b3124b345428d2813:27
tpbTitle: soc_core: remove csr_expose and add add_csr_master method · enjoy-digital/[email protected] · GitHub (at github.com)13:27
_florent__and13:27
_florent__https://hastebin.com/huyeqacame.pl13:27
somlonice, thanks! (you also caught my csr_port.dat_r typo :) )13:35
somloI guess for a complete "motherboard-on-a-chip" we'd also need to expose the interrupt pins...13:45
somlo_florent__: something like this, maybe: https://pastebin.com/22PDGAH915:27
tpbTitle: [Diff] diff --git a/examples/litedram_gen.py b/examples/litedram_gen.py index 9450d39. - Pastebin.com (at pastebin.com)15:27
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_florent__somlo: that could be useful for another generator, but here for LiteDRAM the peripherals/registers involved in the DRAM initialization don't have interrupts16:32
somloI'm trying to generate a sort-of "motherboard-on-chip", i.e. all of LiteX minus the CPU :)17:17
somlostarting with the LiteDRAM generator, which generously throws in the uart "for free"17:17
somlofigured I'd expose the CSRs and interrupts, then I have all I need (working on adding ethernet in there as well)17:17
somloso maybe it won't end up as a patch against the liteDRAM example generator, but I definitely think that's a very useful place to start :)17:19
_florent__:)17:36
somlothat said, since you went through all that trouble to help me out with csr_expose, and since "None" is an option for the litedram example generator, let's at least consider this: https://github.com/enjoy-digital/litedram/pull/8217:46
tpbTitle: examples/litedram_gen: allow direct access to CSR (I/O) registers by gsomlo · Pull Request #82 · enjoy-digital/litedram · GitHub (at github.com)17:46
somlothe exposed IRQs (and ethernet, when I get done with it) can go somewhere else more appropriate, if and when :)17:47
_florent__somlo: yes sure, we can merge this one17:48
keesjwon't the core_config["expose_csr_port"] == "yes" check fail if the property is not defined?18:44
somlokeesj: you're right, let me go google the canonical Python way to handle this (it's not my "native tongue" :) )19:06
somlokeesj: I think I figured it out, thanks for catching it!19:14
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keesjnice19:38
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femtoHowdy! Anyone else experience gateware-flash size issues on the TinyFPGA BX? (GitHub Issue: https://github.com/timvideos/litex-buildenv/issues/137 )22:15
tpbTitle: make gateware-flash "FAILED!" on TinyFPGA BX · Issue #137 · timvideos/litex-buildenv · GitHub (at github.com)22:15
mithrofemto: Hi!22:18
mithrofemto: I have seen this before22:18
femtomithro Where is a good place to start checking? Should I examine tinyprog? Or perhaps litex-buildenv?22:25
mithrofemto: I think the issue has something to do with the byte pattern and tinyusb's usb stack22:25
mithrofemto: It seems to go away if you just change the firmware slightly...22:26
femtomithro: modify the firmware? as in litex-buildenv/firmware?22:27
mithrofemto: Yeah....22:27
femtomithro: Ok, I'll attempt to edit a C header or something, and reattempt "make gateware-flash"22:28
mithrofemto: Maybe...22:28
femtomithro: what type of edits got it working for you? (I'm assuming unused code and comments are parsed out by the compiler, and don't affect the binary)22:42
mithrofemto: Unclear at the moment -- cr1901_modern and ewenz in #timvideos are the people who have played with it the latest22:44
femtomithro: ah ok, I'll go ask22:44
femtomithro: thank you!22:44
mithrofemto: ewen is in the New Zealand timezone22:45
mithrofemto: This person -> https://github.com/ewenmcneill22:45
tpbTitle: ewenmcneill (Ewen McNeill) · GitHub (at github.com)22:45
mithrofemo: Can you try with just the bios rather than micropython?22:46
femtomithro: I'm not familiar enough with litex-buildenv... is there a make command for just the bios or something?22:47
mithrofemto: "unset FIRMWARE" and then "make gateware-flash" is probably the right move22:48
femtomithro: I thought "FIRMWARE" needed to be set to "tinyfpga_bx"... so it shouldn't be set?23:08
mithrofemto: Can you type "make info"23:08
femtomithro: whoops.. I misspoke, FIRMARE=micropython, PLATFORM=tinyfpga_bx23:11
femtomithro:23:11
femtomake info23:11
femto              Platform: tinyfpga_bx23:11
femto                Target: base (default: base)23:11
femto                   CPU: lm32.minimal (default: lm32)23:11
femto               Firmare: micropython (default: firmware)23:11
mithroYeah, try unsetting the firmware value23:32
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