Wednesday, 2019-05-15

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_florent__Dolu: thanks for the link05:37
_florent__Dolu: i think the boot time is directly related to the CPU freq and type of RAM that is used, but yes i should investigate a bit05:38
Dolu_florent__ : Is there a way to get a simulation which include the DDR stuff ? i can then check the wave and what happen on the busses.07:25
keesjperhaps litedram/examples/sim might be a good start  _florent__ mentioned it was possible to test using.. xsim07:38
_florent__Dolu: yes we can simulate with LiteDRAM and a SDRAM model08:09
_florent__Dolu: but for now the capability to initialize the SDRAM model is missing...08:09
_florent__so i would need to add it or have a look directly on hardware08:10
_florent__the boot time of the avalanche board seems really slow compare to the others boards with similar CPU freq/RAM08:12
futarisIRCcloudThe avalanche board was with the old vexriscv...08:12
_florent__but it's using the Microsemi DRAM controller, i haven't tested efficiency/bandwidth with it08:12
futarisIRCcloudI wonder what the boot time is like on a PSRAM based board.08:13
_florent__futarisIRCcloud: i think this Avalanche link use the new VexRiscv: https://risc-v-getting-started-guide.readthedocs.io/en/latest/linux-avalanche.html#08:13
tpbTitle: Running 32-bit Linux on Litex/VexRiscv on Avalanche board with Microsemi PolarFire FPGA RISC-V - Getting Started Guide (at risc-v-getting-started-guide.readthedocs.io)08:13
futarisIRCcloudOh, didn't see they rebuilt it.08:15
keesjfor adding a clock definition.... somewhere the magic happens to add add_clock in the top.xdc (I think depending on the existance of the default_clk_period but there are also cases where the clock is added using platform commands08:19
keesj(in my case the magic does not happen)08:20
daveshahWonder if the boot time on the Avalanche is partly related the the AXI bridge between the SoC and the Microsemi DDR IP08:20
_florent__daveshah: yes that's possible, it would need to be investigated. It seems even the targets with 16-bits SDRAM and slow clock freq are booting faster...08:45
DoluJust one thing to keep in mind about the CPU, is that it is actualy a write-through data cache. So, each software store will end up with one memory request on the wishbone dBus08:57
futarisIRCcloudThe GOWIN / Anlogic FPGAs seem to be cheap too. Sipeed Tang should be able to run vexriscv and linux. 8MB SDRAM on the same IC.09:32
_florent__futarisIRCcloud: thanks, that's indeed cheap09:50
_florent__keesj: you need to use add_period_constraint to add a clock constraint09:53
keesjcool thanks!11:08
keesjhow long is the sim.py test expected to take? (it has been running for a few hours now)12:10
Dolukeesj, which sim exactly ? the linux one ?12:43
keesjwell sim in litedram (examples/sim) that one (running under linux) used the vivado xsim. I think it might be running 4 ever. I interrupted and it shutdow mostly gracefully13:54
keesjhmm it is gone in the main repository https://github.com/enjoy-digital/litedram/commit/b93412bbdc116e4b59023e129103c5ed29bf584413:55
tpbTitle: examples: remove verilog simulation · enjoy-digital/[email protected] · GitHub (at github.com)13:55
keesj 5 days ago13:56
keesj_florent__: I fixed the clock warning and can trace some signals (ODT and BA2 for example) but still not the RAS,CAS,WE signal I am starting to suspect signal integrity problems14:59
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_florent__keesj: i indeed removed the sim, it was not working as commited and was just here to provide an example of how to generate the core and run it with xsim21:56
_florent__keesj: but some modules were missing21:56
_florent__the best is to generate the full core and just simulate it, but i can be a bit slow21:56
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