Monday, 2019-05-13

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_florent__keesj: how is going your ISERDESE2 / DDR project?09:25
keesjI was a hack in the box last week hence not much progress. I was able to capture the ODT signal but was so far not able to capture the cas/ras/we signals.. I do not know why09:27
_florent__ah ok thanks, i was just curious09:28
keesjI will first try understanding/fixing some warning I still have in the code (one about my clocks not well defined and and other about ... on of the d0 d6 needs to be connected09:31
keesjWARNING: [Power 33-232] No user defined clocks were found in the design!09:33
_florent__for testing your code, maybe you should generate pre-defined patterns with the FPGA or an external equipment and verify that you see this with your analysis gateware/software09:33
_florent__this means that you probably forgot to apply a clock constraint to the input clock pin09:34
keesjI first did that with the tinyfpga (until 48Mhz) but not my whole design is synced with the DDR clock09:34
keesjand I for example need to generate a 200Mhz clock for the idelday.09:35
_florent__in your case, you need to apply timing constraint to the system clock and to the DDR clock (if you are using it to sample your data)09:37
keesjI have two boards so  I indeed might be able to connect them togethers. but I also have other things I need to figure out .. like the SSTL135 IOStandard, just grounding or doing a pull up did not produce the expected result either09:37
keesjbut I am quite happy to see that the wishbone serial is working and stuff so .. pretty cool so far09:38
keesjit is kinda crazy how much it working with some basic cut & paste09:43
keesj(and reading)09:46
keesjand .. I gave up (for now) on the 4:1 logic analyzer part. I think it would be a great demo/example code so have a fast logic analyzer09:51
*** felix___ is now known as felix_12:24

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