Wednesday, 2019-05-08

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xobsJust a heads up: I have a Rust-based Wishbone bridge that I'm working on. Currently it can act as a basic devmem2, and can also act as a Wishbone bridge (just like litex_server). Though right now it's only for USB.04:46
xobsNow I'm working on having it act as a gdbserver for Vex, too, which would eliminate the need to run openocd and litex_server together.04:47
futarisIRCclouddaveshah: Is the "liteeth f0009800.mac: Failed to get IRQ" the interrupt stuff you mentioned you mentioned about 20 hours ago?05:13
keesjso rust is then running on the host pc and directly talking to usb using the kernel API ?06:42
keesje.g. urb's06:42
keesjremind me of
tpbTitle: Home · blacksphere/blackmagic Wiki · GitHub (at
xobskeesj: most of the magic is in the `libusb_control_transfer()` function, which is part of libusb.  Such a bridge already exists in litex, but I'm still not sure how to set up pyusb on Windows.06:56
xobsBy porting the bridge to Rust, I have a single executable I can share with people that requires no installation, supporting libraries, or drivers.06:56
keesjI have been dealing with windows and usb but that was really a while ago. just like with linux libusb0.1 v.s. libusb1.0 I think that windows had similar problems. but.. does you implementation despend a c library (libusb or does it perform the call itself directly?)06:59
keesj(I also haven been dealing with libusb on linux and the libusb on android that are just wrappers around the kernel interface)07:00
xobsIt turns out that with, it's possible to statically link the c libraries.07:00
xobsUsing libusb-sys, they actually just dump the libusb source into the libusb-sys directory and define various CPP flags, then add individual C files and generate an output library, which then gets linked to the resulting rlib.07:02
xobslibusb has a winusb backend, so yes, libusb is still just a wrapper around the individual kernel interface.07:02
futarisIRCcloudxobs: If you keep going, eventually you'll end up with something like / ...07:03
tpbTitle: GitHub - ufrisk/MemProcFS: The Memory Process File System (at
keesjIt is just that with GPL even lgpl statically linking does put some requiremetns on your code  about
tpbTitle: FAQ · libusb/libusb Wiki · GitHub (at
tpbTitle: open source - GPL/LGPL and Static Linking - Stack Overflow (at
xobsfutarisIRCcloud: I'm not sure what advantages that brings, but it looks possible?07:08
keesjyea.. don' worry ... be happy.07:09
xobskeesj: I can definitely see that being an issue. fortunately, the API barrier is pretty clear-cut, so if I wanted to swap out the LGPL part for something else that's definitely doable.  Plus, it's open source already, so that part is compatible at least.07:10
keesjI was looking at yesterday or a few days ago (also rust I think)07:12
tpbTitle: GitHub - adamgreig/ffp: fpga/flash programmer (at
tpbTitle: ffp/firmware/src/hal/usb at master · adamgreig/ffp · GitHub (at
xobshandy! I wonder if anyone has gotten Rust building for RISC-V yet...07:14
futarisIRCcloudMainly for fuzzing devices.07:14
tpbTitle: GitHub - rust-embedded/riscv: Low level access to RISC-V processors (at
futarisIRCcloudActually, it went upstream a few months ago...07:15
keesjfutarisIRCcloud: what do you mean by "Mainly for fuzzing devices?"07:16
xobsfutarisIRCcloud: oh cool! I see riscv32imc-unknown-elf target.07:16
futarisIRCcloudIn response to xobs above... Being able to grab memory on a running system, is what ufrisk is doing on Windows machines.07:17
tpbTitle: GitHub - rust-embedded/wg: Coordination repository of the embedded devices Working Group (at
futarisIRCcloudI saw someone running rust in UEFI a few months ago...07:19
futarisIRCcloud looks interesting.07:21
tpbTitle: RISC-V and Rust: Embedded Systems Done Right | Oxidize Berlin Conference (at
daveshahfutarisIRCcloud: yes, that's the same problem07:34
daveshahThe driver for the LiteX interrupt controller needs to be integrated and added to the DTS07:35
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keesjfor the logic analyzer.. I am grabing the data from the serdes into a 4 bit signal. what trick can I used to flatten it again?09:28
keesjcan I perform 4 ticks per sample or similar e.g.
_florent__keesj: you can just use a converter:
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
_florent__in your case:10:17
_florent__data_converter = Converter(4, 20)10:17
_florent__write the data with data_converter.sink valid/ready/data in 4 bit format10:18
_florent__and it will generate data on data_converter.source valid/ready/data in 30 bit format10:19
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keesjI also "discovered" that the analyzer can write in sigrok format.. pretty cool10:38
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keesjI don't understand :(11:05
keesjwhy do I want to go to 20 bits/end up with 30 bits11:08
DoluZnc would be one package to try as soon the ethernet is working ^.^
tpbTitle: buildroot/package/znc at master · buildroot/buildroot · GitHub (at
daveshahDolu: I had the Lynx web browser running on the old Vex/LiteX setup with buildroot (using a rootfs on NFS to avoid a big initrd)13:01
Doludaveshah: Hoo damned XD  Honnestly, i don't know you and others managed to get the old VexRiscv running linux. It realy wasn't implemented with it as a goal, and missed many features XD13:32
daveshahIt was such a horrible hack tbh13:33
daveshahThe new, proper setup is about 10-20x faster13:33
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