Sunday, 2019-05-05

*** tpb has joined #litex00:00
xobsmithro: I really really want to integrate wavedrom into litex.00:44
mithroxobs: Yes01:03
mithroxobs: There is already ...01:04
tpbTitle: sphinxcontrib-wavedrom · PyPI (at
tpbTitle: sphinx-wavedrom/ at master · bavovanachte/sphinx-wavedrom · GitHub (at
xobsI'm thinking we can add parameters to the csr functions that describe various bits and their meanings.01:05
tpbTitle: GitHub - BreizhGeek/wavedrompy: WaveDrom compatible python command line (at
mithroWaveDrom compatible python module and command line. - This tool is intended for people who don't want to install the Node.js environment just to use WaveDrom as simple command line.01:06
xobsOh perfect.01:06
tpbTitle: GitHub - chiggs/mdx_wavedrom: Python Markdown extension for inserting wavedrom waveform diagrams into markdown output (at
mithroxobs: Have you seen and ?01:15
tpbTitle: Symbolator Symbolator 1.0.2 documentation (at
xobsmithro: I haven't, but I'm mostly excited about the register documentation ability of wavedrom, less excited about the waveform stuff.01:16
mithroxobs: Also looks like there is -- This version is not a mere copy of the original one.01:17
tpbTitle: GitHub - LudwigCRON/pywave (at
mithroxobs: If your interested in Latex --> :-P01:19
tpbTitle: GitHub - wifasoi/WaveDromTikZ: An implementation of WaveDrom which outputs TikZ for use in LaTeX documents. (at
*** futarisIRCcloud has quit IRC04:52
*** futarisIRCcloud has joined #litex06:30
*** Dolu1990 has joined #litex07:30
tpbTitle: Add support for ECP5 Versa-5G with Yosys/nextpnr/Trellis by daveshah1 · Pull Request #1 · enjoy-digital/linux-on-litex-vexriscv · GitHub (at
daveshahOne strange issue I've noticed is that when the system is cold (metaphorically if not thermally), occasionally the TFTP boot fetches an incorrect (too small) number of bytes - this seems to happen with both Diamond and Trellis09:32
daveshahdoesn't ever happen once it's been run once or twice09:32
daveshahnot sure if you've ever seen anything like this before?09:32
daveshahI also notice it prints a main RAM size of 262144KB which is double what it should be (but memtest passes, and the DTS only specifies 128MB, so it has no bearing on functionality)09:33
keesjwhat is the 25Mhz initial clock ?09:35
daveshahThis controls the startup FSM that ensures the DDR clocks are properly synchronised09:36
daveshahIt's a bit of an ECP5-specific idiom09:36
Dolu1990daveshah: Nice :D09:46
Dolu1990Maybe it is because the the IO range specification of the load/store ?09:47
tpbTitle: VexRiscv-verilog/GenCoreDefault.scala at master · enjoy-digital/VexRiscv-verilog · GitHub (at
Dolu1990Ahh no, 0xB map the ethernet09:48
Dolu1990I mean, the bootloader use 0xB0000000 or 0x30000000 to access the ethernet ?09:49
*** Dolu1990 has quit IRC10:50
*** Dolu has joined #litex11:05
futarisIRCcloud does look good daveshah ...11:56
futarisIRCcloudI wrote something for the ecp5, using diamond yesterday, but couldn't get it to run (because of the license I was using)11:56
futarisIRCcloudIt should be trivial to add ulx3s support, since that's already in litex.11:57
*** Dolu has quit IRC12:38
*** Dolu1990 has joined #litex12:42
*** Dolu1990 has quit IRC18:28
*** Dolu has joined #litex18:30
_florent__daveshah: i already had the netboot issue on the arty, so that's probably not specific to ecp5, i'll have a look19:24
daveshahAh, interesting19:25
daveshahEven with the Versa board powered off for a long time, it didn't seem to come back (but my computer was on the whole time). It almost seems related to the TFTP server being "cold"19:26
tpbTitle: GitHub - asyncvlsi/AMC (at
xobsmithro: looks brand new! Similar to openram in that it's a tiler?20:56
mithroxobs: No idea, only found it 5 minutes ago :-P20:56
xobsOoh, it does have one ruleset20:56
tpbTitle: Yale Asynchronous VLSI (at
mithroAMC is an open-source asynchronous pipelined memory compiler. AMC generates SRAM modules with a bundled-data datapath and quasi-delay-insensitive control. AMC is a Python-base, flexible, user-modifiable and technology-independent memory compiler that generates fabricable SRAM blocks in a broad range of sizes, configurations and process nodes. AMC generates GDSII layout data, standard SPICE netlists, Verilog models, DRC/LVS20:58
mithroverification reports, timing and power liberty models (.lib), and abstract placement and routing models (.lef).20:58
xobsRight now it looks like they target
tpbTitle: MOSIS Layer Map for SCN3ME and SCN3ME_SUBM (at
*** Dolu has quit IRC22:52
*** Dolu1990 has joined #litex22:56
*** Dolu1990 has quit IRC23:45

Generated by 2.13.1 by Marius Gedminas - find it at!