Thursday, 2019-05-02

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keesj\o/ I am at least getting something!06:52
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keesjmy plan now it to start the system from the ddr clock to be synchronized with it I hope I won't run into the same type of issues12:57
keesjcan I create a crg13:16
keesjwhen I have no Soc?13:16
keesjI see GRC is "just" a submodule of a module or is it more complicated?13:16
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keesjso adding GRC as submodule is enough to change the sys_clk apparently :P.. cool14:08
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* somlo goes grepping for where he's supposed to provide a useful string to replace "Unknown" :)17:03
somlokeyboard i/o doesn't work yet, but at this point I think it's a "Simple Matter of Programming" :)17:04
somlo_florent_: thanks again for the axi2wb fixes, it was the software trapping due to accessing the wrong Rocket risc-v CSR registers17:06
_florent__somlo: great!17:07
somlo_florent_: I'm impressed at just how little hackery was actually needed to get it going -- LiteX Rocks!!! :)17:08
* somlo found the #ifdef in main() where he should add printf "RocketRV64[imac]"17:10
somlonext on the agenda is getting the simulation to accept keyboard input (most likely still just a software thing)17:11
_florent__VexRiscv new MMU also rocks: :)17:14
tpbTitle: untitled - asciinema (at
tpbTitle: GitHub - enjoy-digital/linux-on-litex-vexriscv: Experiments with Linux on LiteX-VexRiscv (at
_florent__^ miaou_17:15
miaou_Hi, sorry for my name, i'm Dolu17:17
miaou_Hoo nice :D17:18
miaou_wtf XD17:19
miaou_GG !17:19
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DoluHow the synthesis is running ?17:22
DoluHoo 100Mhz17:23
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DoluWasn't to much of a pain to get it working ?17:24
_florent__no, i just adapted things progressively with the simulation (mostly reusing LiteX peripherals and adapting the emulator code)17:28
_florent__then i tested on hardware and it just worked :)17:28
Dolu5.0.9, Yeahhhhhh 4.20.17 is so borring ^.^17:29
DoluNice :D17:30
Doluit was probably pleasant :p17:31
_florent__i just wanted to be sure it was working with upstream version of all the tools :)17:31
DoluAbout synthesis, things were looking good ?17:32
Dolufrequancy, area usage and stuff like this ?17:32
_florent__timing is fine yes on the XC7A35T of the Arty17:35
_florent__here is the resource usage:
DoluHmm there is synthesis issues17:37
Doluthe instruction cache and data cache are way too big17:37
DoluIt didn't all infered the caches ram as ram blocks17:38
_florent__ok, i can look at the vivado report17:39
_florent__btw, if you want to look, you can generate the bitstream by just executing:
tpbTitle: linux-on-litex-vexriscv/ at master · enjoy-digital/linux-on-litex-vexriscv · GitHub (at
DoluAs a estimate, the instruction cache should be about 200 lut, and the data cache about 600 lut (with atomic)17:39
DoluSure, i will look at it17:40
DoluI can reproduce the issue, thanks for flow ^^. When i have a fix i will tell you.18:12
Dolu^ _florent__  The VexRiscv.v was generated with sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux" ?18:16
DoluAlso forcing using ram blocks for the caches reduced the LUT usage by 800 LUT, but there is still something wrong, still 1K lut getting somewhere it shouldn't, especialy the instruction cache.18:18
DoluAhhh, could have been linuxMinimal, should save about 300 LUT, i will give a try18:23
tpbTitle: VexRiscv-verilog/GenCoreDefault.scala at master · enjoy-digital/VexRiscv-verilog · GitHub (at
daveshahJust tried building for Versa ECP5 and it still meets timing at 75MHz which is good (usage is horrible because of unsupported DSP inference, but we'll hopefully sort that soon). Will test on hardware tomorrow and submit a PR if it is working18:24
daveshahBoot time looks about 10-20x faster than with the previous MMU which is awesome18:25
DoluHoo good :)18:25
DoluLet's me know how things goes !18:25
daveshahHad to reduce emulator ram size from 0x10000 to 0x8000 because it ran out of BRAM18:25
DoluAlso, Multiplication can be changed to be iterative without DSP18:25
Dolu(rebooting my PC)18:26
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xobsdaveshah: DSP inference? Do say more.  Are those similar DSP blocks to the ICE40?18:38
daveshahNo, they are quite different18:52
daveshahBut there should be some more work on DSP stuff in general soon (in particular things like splitting larger multiplies)18:52
daveshahOnce that's moved on a bit I'll look at adding ECP5 support18:53
xobsWell hooray!  Looking forward to that.18:54
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Dolu1942^ daveshah adding --singleCycleMulDiv false to the arguments of the VexRiscv generation would solve it.19:17
_florent__Dolu1942: yes, i was using sbt "runMain vexriscv.GenCoreDefault --externalInterruptArray=true --csrPluginConfig=linux"19:33
Dolu1942Hoo about the emulator memory requirements, they are oversized21:02
Dolu1942The stack do not need to be big at all21:02
_florent__yes, i will reduce that21:06
Dolu1942Also, one thing which isn't implemented in the machine mode emulator, is the unaligned access emulation21:43
Dolu1942Currently if a unaligned access is done, where ever it is, it will come back t the machine mode and exit everything.21:44
Dolu1942Should the emulator emulate the unaligned load/store ? or it should propagate the exception to the supervisor ?21:45
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Dolu_florient__ Going from CSR linuxFull to linuxMinimal reduced the LUT occupancy by 800 XD23:14
DoluCombined with the ram block forcing, the total VexRiscv LUT usage is downto  266523:14
DolulinuxMinimal    vs linuxFull
tpbTitle: VexRiscv/CsrPlugin.scala at master · SpinalHDL/VexRiscv · GitHub (at
DoluAhhh mybad not exactly23:26
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