Wednesday, 2019-05-01

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futarisIRCcloud[email protected]/msg610224.html01:54
tpbTitle: [Qemu-devel] [PATCH for 4.1 v3 0/6] RISC-V: Allow specifying CPU ISA via command line (at
futarisIRCcloud[email protected]/msg611889.html01:55
tpbTitle: [Qemu-devel] [PATCH v1 0/6] RISC-V: Add properties to the CPUs (at
futarisIRCcloudIntel x86 on RISC-V - Qemu ception02:30
keesjI need to find a way to speedup my experiments. I am starting to get somewhere but it takes minutes to compile the bit file and I can not really do anything but wait else I get into a context switch06:44
futarisIRCcloudlitex simulator (with the bridge) ???07:29
keesjI did a little testing using python when following the tutorial and tried to understand a few times how to test the serdes but I still don't quite get it09:26
keesj I am trying to follow the xapp1017 notes (my current code)09:26
tpbTitle: Ubuntu Pastebin (at
_florent__keesj: yes, with vivado, even a very simple design takes a couple of minutes to compile...10:27
_florent__keesj: this is one of the case where open-source toolchains are really interesting, a very simple design takes seconds and it ease doing multiple iterations...10:28
_florent__i see that you also reduced your design to something small, so you will not gain a lot in compile time10:29
_florent__keesj: you are using an IDELAYE2 before the ISERDESE2, so p_IOBDELAY="NONE" is wrong. XAPP1017 is using "IFD"10:37
keesjI was using ifd but ... then I get an other error about my O port (will compile and test again)10:45
keesjwith ghdl (using vhdl and good test benches) I was also able to do quick tests (when doing my can bus stuff) but once I start using special blocks.... not great10:47
keesjwith IFD I am getting ERROR: [DRC PDIL-1] Invalid Site Configuration: Invalid configuration for site ILOGIC_X0Y76. Reason: Site pin to site pin route-thru requires conflicting attribute enum values for user logic element 'ISERDESE2 in site 'ILOGIC_X0Y76'. Attribute 'IOBDELAY' is programmed to 'IFD' but needs a value of 'NONE' for the route-thru.10:47
keesjit has been almost a week now of reading . "a ha" moments" and trial and error. One thing that might be more usefull for the general public is if I first try to create a damm fast logic analyzer using internal clock and iserdes210:50
keesjand my understanding of the blocks is not good enough to write a stub10:56
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_florent__keesj: i just had another look at your code19:22
_florent__your issue is probably due to the fact that you are connecting nwe to the ISERDESE2 and LiteScope19:23
_florent__this signal can only go to the ISERDESE2, it's not possible to observe it with LiteScope19:24
keesjI will defenitely give it a try. I think I tried this already but I did not really inspect the generated to to know what is going on under the hood. in this case I would need to not define a self.nwe but only directly use or similar19:47
keesjI also was thinking perhaps I need to take little baby steps . first capture 8 lines at 100 Mhz (the curent setup) next try the same at 200Mhz ,then move to 400Mhz serdes 1:2 SDR mode (all as example of the logic analyzer)19:50
keesjIt would be very helpfull for the sustainability of my project to have a litle more progress19:51
keesjthe code does generate something like assign mux_endpoint1_payload_data = {nwe_buf, ddr_nwe} indeed19:56
keesj_florent__: the warning is now indeed gone... I can not test it right now crossing fingers!20:03
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