Monday, 2019-04-29

*** tpb has joined #litex00:00
futarisIRCcloudhttps://gitlab.com/theseus-cores/theseus-cores00:23
tpbTitle: Theseus Cores / Theseus Cores · GitLab (at gitlab.com)00:23
keesjhmm sdr+fpga .. so nice..08:26
keesjI also have a pluto sdr module with lots of documentation. it is really amazing as it does so much stuff (pc communication, it is running a full linux, it has an fpga(psoc I think) , the analog modules and the RF front end08:28
keesjhttps://wiki.analog.com/university/tools/pluto08:29
tpbTitle: ADALM-PLUTO Overview [Analog Devices Wiki] (at wiki.analog.com)08:29
_florent__keesj: indeed, the pluto is really interesting for the price08:36
*** futarisIRCcloud has quit IRC08:48
keesjthe only "down side" is that it can not transmist high power.. for me this is probably a good thing.. (I have a few more SDR's).09:30
keesjAn other project I spend time one before this FPGA project I am currently working on is the chipwhisperer (This is a SAM3U + Spartan 6 + ADC for side channel analisys) the board itself is open hardware and the sources are also available. It is just waiting for litex to provide cool protocol and triggering features09:33
keesjthe sides from osda look like a nice overview of litex/fhdl/migen https://osda.gitlab.io/19/1.1-slides.pdf09:33
keesjif there is a workshop somewhere I would probably join09:34
*** futarisIRCcloud has joined #litex10:02
_florent__keesj: yes these devices are generally not intended to transmit high power. It's fine for testing in the lab.11:44
_florent__keesj: doing a workshop could be fun, i know a few others people that could be interested, i'll see in the future if i can organize one11:49
keesjI am currently also writing a small game in verilog (a modification from pong from fpga4fun). over the week-end I replaced the padle code with something that use an ultra sonic distance sensor.12:44
keesjI am will next try to get two sensors working (one at the time) but perhaps can also do some more radare type stuff12:44
keesjthis is on the tinyfpga and inspired by older videos from Jeri Ellsworth I think it would also be fun to use the VGA output as scope12:45
keesjand because it was kingsday in .nl there was a huge flee market in Amsterdam and I got hold of a second px1000 device https://www.cryptomuseum.com/crypto/philips/px1000/index.htm12:47
tpbTitle: PX-1000 (at www.cryptomuseum.com)12:47
keesj(I might .. if I ever get to it implement it in fpga)12:48
_florent__nice, feel free to share you progress here :)12:50
keesjit remains kinda slow ...12:53
keesjafter more reading and trying last week I am still working on the serdes. today I "discovered" that not all high speed input pins of the arty can be used as clock source12:59
keesjI also am reading the xapp1017 app notes on the serdes.13:00
keesjif I will try to clock in DDR mote at at 48Mhz clock (96 Mbit/s)13:02
keesjand push this to LiteScope13:02
keesjalso by reading the SelectIO resource I am starting to see the pattern between the "self.special" items and the generated code13:04
keesjit would be nearly impossible to understand the python code without this documentation13:04
keesjfuther more.. for my design I am thinking it might be best to use the incomming ddr clock to clock the whole system (my ddr clock is at 530 Mhz) but I think the A7 can only do about 450 Mhz internal logic13:06
keesjturtles all the way down13:07
_florent__your internal logic will not run at the DDR clock since you are using IOSerdes in 1:8 mode, but yes that's still challenging since in LiteDRAM the default DDR clock is 400MHz on Artix713:17
_florent__i remembered testing Artix7 DRAM with higher frequencies (at least 500MHz DDR clock)13:18
keesjI can't even use 1:8 mode I probably need 1:2 for more real time capabilities(less latency)14:03
keesjthe arty page states 256MB DDR3L with a 16-bit bus @ 667MHz14:08
keesjthat is the clock rate right (e.g. the bit rate is 16 * 667 * 2) ?14:09
keesjor does this require some xilinx magic?14:10
somlolitedram_gen.py is highly Xilinx-centric :)14:23
* somlo trying to "translate" it into something that'd work on ecp5versa...14:23
_florent__somlo: that should help you integrate the rocket CPU: https://github.com/enjoy-digital/litex/commit/5c1d9805400d1593ebe6cd42f6948af735f02de9 :)14:59
tpbTitle: soc/interconnect/axi: add burst support to AXI2Wishbone · enjoy-digital/[email protected] · GitHub (at github.com)14:59
_florent__somlo: the AXIBurst2Beat was already well tested in LiteDRAM, so it should work without too much troubles15:00
somlo_florent_: oh cool, back to plan A, then :) Just started working on an ecp5 specific version of litedram_gen.py, with the long-term goal of re-factoring it to the point where the xilinx-specific (or lattice-specific) bits are in the *_config.py files :)15:03
somlobut now I can't *not* go back to trying out straight-forward rocket integration again :)15:04
_florent__yes sorry, for now litedram_gen was only for Xilinx FPGA15:06
_florent__having support for the others family would be really nice15:07
_florent__if you have a   patch for ECP5, i'm happy to merge15:07
_florent__otherwise for the AXI2Wishbone, i also have a need for it, that's why i did it, but that would be interesting to see if it allow you to integrate rocket15:08
somloabout that, it looks like the standalone litedram module handles clock generation internally, and outputs a "user" clock that goes to the CPU and other non-LiteX SoC blocks15:08
_florent__yes because in most of the cases the CPU will just use the DRAM clock15:10
_florent__CPU = (not the embedded CPU but the CPU of the SoC where the LiteDRAM core is integrated)15:10
somlowait, user_clk is the same as what the litex embedded cpu uses, and it's different from e.g. ddram_clk_p15:15
somlowhich is fine, the fastest I got Rocket to run on ecp5 was 20MHz, and I'm totally fine with the ddram going faster than that15:15
_florent__but i'm not sure we tested the DRAM controller on ECP5 below 50MHz15:21
_florent__and you'll need to run your Rocket CPU with the provided user_clk15:22
somlowait, I'm getting confused :)15:23
somloI thought the DRAM itself is in a different clock domain from user_clk15:24
_florent__it's a different clock domain but synchronous and dram_clk = 4*user_clk15:25
somlooh, so if you specify a low user_clk you get a correspondingly lower dram clock, because hardcoded 4?15:26
somloeasy test, I can try building a vexriscv litex soc for the versa at 20MHZ, see if it passes dram test :)15:27
_florent__yes i would recommend testing before15:30
*** futarisIRCcloud has quit IRC15:32
somlook, so simply changing sys_clk_freq doesn't work below 50MHz here: https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/versa_ecp5.py#L8216:22
tpbTitle: litex/versa_ecp5.py at master · enjoy-digital/litex · GitHub (at github.com)16:22
somlobut then, there's this, a few lines further down: https://github.com/enjoy-digital/litex/blob/master/litex/boards/targets/versa_ecp5.py#L9716:23
tpbTitle: litex/versa_ecp5.py at master · enjoy-digital/litex · GitHub (at github.com)16:23
somloapparently the rate is 1:2, wonder what will happen if I change that to 1:416:23
somloI suppose I could find out if I dug around long enough, but what's the preferred target dram clock interval for MT41K64M16 (the dram chip on the ecp5 versa)?16:26
_florent__on ECP5, the controller has only been validated at 1:4, 1:2 would need specific work to work16:29
somloso how come it's 1:2 in the upstream sources?16:29
somloand it works (with 1:2 and 50..75 MHz) too, so I'm not complaining, just confused :)16:31
_florent__ah no sorry, we only validated 1:216:31
somlook, so far it failed at 25Mhz and 1:4, trying 30Mhz next :)16:32
_florent__1:4 won't work16:32
somlolike, not at all?16:32
somlook, might as well not waste time on it, then16:32
_florent__it's not possible with the IOs of the ECP516:33
somlook, so that's good to know, if/when I get Rocket to work with AXI under verilator, I'll have to get it to run at min. 50MHz16:34
_florent__if you want to test/integrate rocket, it's maybe better to use the other xilinx board you have in a first time16:34
somloI have a nexys4ddr, but I hate Vivado :)16:34
daveshahRunning at a lower frequency might be possible by changing the READ pulse position16:35
daveshahhttps://github.com/enjoy-digital/litedram/blob/master/litedram/phy/ecp5ddrphy.py#L46216:35
tpbTitle: litedram/ecp5ddrphy.py at master · enjoy-digital/litedram · GitHub (at github.com)16:35
somlodaveshah: I'm writing that link down for future reference :) Right now it looks like some bit passing through a shift register, and dqs_read is asserted when the bit passes through a certain 2-bit window in that register :) No clue as to how I'd change that, but before spending time on this mystery, I'd first have to get Rocket working in simulation anyway :)16:52
somlo_florent_: still triggering the (same) AXI assertion inside rocket :( Something about an AXI RVALID response arriving before the corresponding AXI ARVALID request being sent...18:33
_florent__somlo: can you share you simulation code so that i can have a look?19:03
somlosure thing. I just sent a bunch of PRs to factor out the (hopefully) "uncontroversial" mods to litex, litedram, and tapcfg (vexriscv simulation and nexys4ddr & ecp5versa synthesis still work perfectly fine after these patches)19:17
somloso I'll then only have to point at Rocket-specific hacks, which should be easier to consider once the "noise" has been factored out :)19:18
*** futarisIRCcloud has joined #litex22:12

Generated by irclog2html.py 2.13.1 by Marius Gedminas - find it at mg.pov.lt!