Saturday, 2019-04-27

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tpbTitle: Standardizing `cpu_variants` and adding lots of documentation by mithro · Pull Request #175 · enjoy-digital/litex · GitHub (at
mithro_florent__: ^00:11
mithrofutarisIRCcloud: ^00:11
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futarisIRCcloud_florent_ : looks good.09:32
tpbTitle: Commits · enjoy-digital/linux-on-litex-vexriscv · GitHub (at
futarisIRCcloudI couldn't figure out how the sbi and peripheral addresses are being set in that tree, though. Are the CSRs just being generated from the order of the definitions?09:34
futarisIRCcloudCONFIG_SIFIVE_PLIC=y - Is Interrupt controller you mentioned (yesterday) actually compatible with the SIFIVE PLIC?09:44
tpbTitle: linux/irq-sifive-plic.c at master · torvalds/linux · GitHub (at
_florent__futarisIRCcloud: just for info, for now i was just trying to reproduce the spinal simulation in the litex environment09:46
futarisIRCcloud - sec 809:46
_florent__futarisIRCcloud: i don't think the SIFIVE_PLIC is really needed in buildroot for now09:46
futarisIRCcloudAhh, ok. I thought you were wiring it up the same way as renode / antmicro.09:47
_florent__no, here we are using the the last version on VexRiscv and just want to redo the process to understand things while doing it09:48
tpbTitle: linux/earlycon-riscv-sbi.c at master · torvalds/linux · GitHub (at
tpbTitle: linux/hvc_riscv_sbi.c at master · torvalds/linux · GitHub (at
tpbTitle: linux/sbi.h at master · torvalds/linux · GitHub (at
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