Thursday, 2019-04-18

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keesjsomlo: when I was learning vhdl I had a great time doing test based development but in the last couple of month switching to verilog and migen I have a hard time determining how to start06:22
keesjand .. I don't know how to test something like a serdes.06:28
keesjsomlo: what is  your background/experience in FPGA development?07:31
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_florent_keesj: to simulate a serdes, you can use xsim10:04
_florent_keesj: you generate a the top level with migen, and then stimulate if the way you would do with a traditional verilog approach10:04
_florent_keesj: here is a testbench that could be useful for you:
tpbTitle: liteiclink/ at master · enjoy-digital/liteiclink · GitHub (at
keesjvery cool10:39
somlokeesj: my background is mostly in software, networking, and sysadmin. I re-took a digital design /comp. arch ECE course sequence at the uni where I work (they use Verilog).13:32
somloI'm a relative n00b when it comes to migen (and Chisel, for that matter)13:33
keesjI am kinda somewhere in between everything.16:32
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