Wednesday, 2019-04-17

*** tpb has joined #litex00:00
keesjmy up5k based board is finally blinking10:37
keesjNow I will need to implement the usb stack thingy10:37
keesjsteal from fomu / litex10:38
somloTrying to debug a new cputype using "", and Verilator crashes with "%Error: Verilog called $test$plusargs or $value$plusargs without testbench C first calling Verilated::commandArgs(argc,argv)".14:02
somloI have some (not a lot) of experience with Verilator, but the testbench c++ files I used to write had a "main()" function whose "argc" and "argv" I could use to call into "Verilated::commandArgs()".14:02
somloThe litex-generated gateware simulation directory has "dut_init.cpp", and there's also "litex/build/sim/core/veril.cpp", but neither have a "main()" function from where I could call "Verilated::commandArgs()" -- any ideas?14:02
somlonvm, figured it out, preparing a PR :)14:38
tpbTitle: build/sim/core: Initialize Verilator commandArgs by gsomlo · Pull Request #163 · enjoy-digital/litex · GitHub (at
_florent_somlo: thanks, it's merged17:26
somlo_florent_: thanks! Now on to making sense of what's REALLY wrong with what I'm trying to do :)18:05
keesjI see having no board is bringing good to the community18:07
somlokeesj: I'm assuming if I tried to program the board with what I have right now, it'd be a bitstream-based implementation of a brick18:09
somloso one way or the other, simulation is a necessary step :)18:10

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