Tuesday, 2019-04-09

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keesjdoes platform.request remove the resource from the resource list? (e.g. I can't call platform.request("clk100") twice?06:50
_florent_keesj: hi, have you been able to get your litescope design working?09:09
_florent_keesj: indeed, platform.request will remove it from the resource list, but you can do platform.lookup_request("clk100")09:09
_florent_keesj: to have access to the ressource that was already requested09:10
keesjI have it working but the code ain't very nice https://paste.ubuntu.com/p/RHmWQ5wP58/09:12
tpbTitle: Ubuntu Pastebin (at paste.ubuntu.com)09:12
keesjspecially starting line 87 (messing around createing the csr and analyzer csv)09:13
keesjThe thing is that I want to start using the input serdes2 (and clock my signals on an external differntial input clock)09:15
keesjI want to snoop the ddr clock and we,car,ras and cs line of a memory chip running at 500 ish Mhz09:16
keesjhence I have been looking at the litedram controller and the liteiclink09:18
keesjit is all an impressive amount of code but I hope iserdes2 + scope is a good start.09:19
keesjor perhaps https://github.com/enjoy-digital/liteiclink/blob/master/sim/serwb.py09:22
tpbTitle: liteiclink/serwb.py at master · enjoy-digital/liteiclink · GitHub (at github.com)09:22
_florent_keesj: as a first step, getting the capture working and hook that up to litescope if a first good step yes09:27
_florent_keesj: once you'll have that working, if you need more capture depth, you will have different possibilities09:28
_florent_keesj: buffering in DRAM, outputing over ethernet, ...09:29
_florent_a good start for you PHY would be to reuse the ISERDESE2 that is used for the DQ in litedram/s7ddrphy09:31
_florent_make it run continously09:31
_florent_and sample the commands with it09:31
_florent_to sample the data, you will need to use DQS or use the DDR clock and adjust manually some delays09:33
acathla"but you can do platform.lookup_request("clk100")" Wow! Is that documented somewhere?10:47
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keesjis there an example of using the connectors (pmod for example?) and .. if I use a differential pair will I need to rename the pin numbers to _p and _n ?13:30
_florent_acathla: not sure it's documented...16:45
_florent_keesj: here is an example using the connector, here we are defining the HPC FMC as a connector: https://github.com/enjoy-digital/litex/blob/master/litex/boards/platforms/kc705.py#L28816:46
tpbTitle: litex/kc705.py at master · enjoy-digital/litex · GitHub (at github.com)16:46
_florent_keesj: and using the connector name here: https://github.com/enjoy-digital/litesata/blob/master/examples/platforms/kc705.py#L616:47
tpbTitle: litesata/kc705.py at master · enjoy-digital/litesata · GitHub (at github.com)16:47
_florent_keesj: this should also show you how to use it with a differential pair16:48
keesjI don't quite yet understand it but coool17:29
keesjOk. so I need to register an exention and give it the new pin mapping and a reference to the connector using the  Pins("name:name")18:30
keesjis it intentional that litsata is not part of https://github.com/enjoy-digital/litex/blob/master/litex_setup.py#L2119:24
tpbTitle: litex/litex_setup.py at master · enjoy-digital/litex · GitHub (at github.com)19:24
keesjI think I got it working but I did have to change the syntax of the pmod a little e.g. https://pastebin.com/gR5vZz2N20:14
tpbTitle: ("pmodb", "E15 E16 D15 C15 J17 J18 K15 J15"), ("pmodc", { "pin - Pastebin.com (at pastebin.com)20:14
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