Saturday, 2019-04-06

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xobssomlo: I actually just set stuff up for Foboot.05:25
xobsEverything is self-contained in -- you might be interested in third_party/libbase/crt0--vexriscv.S05:26
tpbTitle: foboot/sw at master · im-tomu/foboot · GitHub (at
xobsI'm not sure why they have all those nops.  I'm going to try removing them.  Maybe it's a caching thing?05:26
xobstrap_entry probably doesn't need to be marked .global, but it'll generate a symbol so the debugger can read it.05:27
keesjxobs: it looks like a jump table . e.g. when the CPU gets an exception (or starts) it normally jumpt to an address in memory (the first one is typically the start addres) . I did some searching around in the code but did not find what the other addresses are supposed to be06:20
keesjnormally for debug the nops are replace by jump/branch to current address . the readme has some hint on the resetAdress (ans so does some asm samples) in the code06:22
keesj also has some notes (this is probably simply part of the risc v specs)06:27
tpbTitle: riscv-notes/ at master · slavaim/riscv-notes · GitHub (at
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xobskeesj: that's a good guess.08:06
xobsmaybe it could also be from the lm32 crt0.S, which is also 8 instructions (with two nop at the end)?08:07
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somloxobs: thanks, I'll have a look -- turns out there's a bunch more stuff like per-arch functions for flushing [i|d]caches, etc. scattered throughout the headers that I need to come up with12:04
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