Thursday, 2019-04-04

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keesjBeen reading the ddr3 code and learning a lot. it remains intimidating/feature full so far11:53
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somlo_florent_: if I try changing the litex mem_map to use "rom" at 0x1000_0000 and "sram" at 0x1000_8000, and the resulting SoC "doesn't work" (no visible uart activity using vexriscv on nexys4ddr or ecp5versa)14:42
somloam I looking for the rom address being accidentally hardcoded somewhere else in the code base, or is there any other potential problem I should assume?14:42
_florent_somlo: each mem_map region should have a size of 256MB (0x1000_0000), there is a limitation on that14:44
somloso if I want to free up 0000_0000 to 1000_0000 (rocket really really wants that for its own purposes), I should do 1000_0000 and 2000_0000 instead of going for smaller regions...14:44
somlothanks, let me try test that out real quick :)14:45
somloyeah, looks like sticking to full 256MB regions works -- thanks again!14:53
somlo_florent_: is that enforced by how slave wishbone interface addresses are decoded here: ?15:10
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
_florent_somlo: yes that's the limitation15:33
mithroLiteX/VexRiscv running Buildroot with Python on Renode22:06
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