Thursday, 2019-03-21

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futarisIRCcloud_florent_: Is the latest VexRiscV linux as per ?08:15
tpbTitle: Linux on VexRiscv · Issue #60 · SpinalHDL/VexRiscv · GitHub (at
_florent_futarisIRCcloud: i haven't tested the latest changes myself yet, this is still very experimental, we now need to discuss and merge things cleanly11:05
xobsfutarisIRCcloud: I've been playing with smaller Vex core for Fomu, so _florent_ added a way to manually override the verilog source for the cpu. It's super handy.12:08
somloWhat would be the least painful way to add rocket-chip as one of the litex.soc.cores.cpu options? Out of the box, Rocket exposes AXI interfaces for RAM and MMIO -- could litex just use that, or would it make more sense to add direct wishbone support to rocket first?13:57
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_florent_somlo: for the ram, you can have AXI port with LiteDRAM, for the MMIO, if it's not doing bursts you can use the AXI to Wishbone module:
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
somloso let's say I add a rocket folder to litex.soc.cores.cpu; there will be a "class Rocket(Module)" with an __init__ method16:02
somlowhich will have to set self.ibus and self.dbus16:02
somlowill those have to be wishbone interfaces (so whatever the core's verilog exposes had better be translated to wishbone first) ?16:03
somloso far all existing cores use wishbone, so I'm kinda assuming that to be the case (would love to be wrong though :) )16:04
_florent_somlo: the infrastructure is not handling AXI natively yet, so the easiest way for now if probably to provide a Rocket Module with wishbone bridge already integrated16:45
_florent_this way, you'll be able to reuse this Module with the existing infrastructure16:45
_florent_if you want to support AXI natively, you'll need to modify SoCCore/SoCSDRAM to handle that16:46
_florent_i'm also planning to do it in the future, i'll be happy to help if you want to go that way16:47
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