Friday, 2019-03-08

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keesjhow can i learn about the symulator?06:59
keesjsimulator that is06:59
_florent_keesj: if you want to use the python simulations, you want follow
tpbTitle: fpga_101/lab002 at master · enjoy-digital/fpga_101 · GitHub (at
_florent_keesj:  if you want to use the verilator simulator, you can look at and execute it07:07
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at
_florent_it will just build as a classic target and will print the bios in your terminal07:08
keesjI had time yesterday again to start looking into litedram and saw the ddr simulation files also hence wondering about that07:23
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somlo_florent_: if I generate a standalone litedram controller (e.g., setting "cpu" to "None" in examples/, is the initialization FSM automatically done in the gateware?21:34
somloI notice the normal "external" dram_* signals, but also a set of "init_done" and "init_error" wires, and none of the (presumably large-is) set of wires that would allow an external CPU to manipulate initialization via MMIO registers21:36
somlo* large_ish set of wires21:36
somlohmmm, digging through the generated verilog, init_done is assigned from soc_init_done_storage, which in turn is initialized to 0 and never changed...21:38
somloso, the question is, can I generate a standalone litedram controller which exposes the necessary MMIO registers that I could manipulate to initialize it from a CPU that's not generated as part of LiteX ?21:39
_florent_somlo: you can but this is not handled by the example design now22:39
_florent_to do that, you need to set CPU to None, create a wishbone bus, add it as master and expose it22:39

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