Tuesday, 2019-02-26

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xobsHi hi10:15
acathlaI have a SoC with only a wishbone bridge with uart. It works with some basic CSR10:16
acathlaI have a (migen) Memory module I would like to write to and read from the UART, what's the best way to do this?10:18
acathlaI found a CSRMemoryRegion in the sources, but i'm not sure it does anything usefull, and there is no doc or example or comment as usual :(10:19
_florent_acathla: you can use this: https://github.com/enjoy-digital/litex/blob/master/litex/soc/interconnect/wishbone.py#L63010:22
tpbTitle: litex/wishbone.py at master · enjoy-digital/litex · GitHub (at github.com)10:22
_florent_you can define your wishbone memory like this: https://github.com/enjoy-digital/versa_ecp5/blob/master/versa_ecp5.py#L22210:25
tpbTitle: versa_ecp5/versa_ecp5.py at master · enjoy-digital/versa_ecp5 · GitHub (at github.com)10:25
_florent_but instead of specifying the size of the SRAM, just pass your actual memory10:25
_florent_you will also have to define your memory in mem_map10:26
_florent_and register it10:26
_florent_as done for firmware_ram in the link10:26
xobsIs there a recommended CPU to use with litex?  I know it defaults to lm32, but is that still the preferred core?11:19
acathla_florent_, thank you, it does not work yet. What's the difference between SoCCore and SoCSDRAM? Your example uses SoCSDRAM but mine was not.11:28
acathlaI have the same error with both : ...soc_core.py", line 206, in __init__ \\ self.register_mem("sram", self.mem_map["sram"], self.sram.bus, integrated_sram_size) \\ KeyError: 'sram'12:10
xobsacathla: from what I understand, SoCSDRAM includes external DDR, so it includes things like link training.12:24
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acathlaxobs, ok, useless for my bare tinyfpga12:57
keesjyou are playing on the tinyfpga ?13:07
acathlaThe _bx yes13:23
_florent_xobs: lm32/mor1kx are working fine but i'm switching to vexriscv progressively14:04
_florent_xobs: picor32 can be interesting for some specific cases, but vexrisc has better performances/resource usage and more configurations14:05
xobs_florent_: the question has to do more with the compilers that I target. I have a riscv toolchain that I've built for Raspberry Pi, and I'm wondering if I should take the effort to build an lm32 one.14:06
_florent_if everything works fine with a riscv cpu for you, i would just use that14:07
_florent_acathla: you need to add your sram to the mem_map, as it's done here for firmware_ram: https://github.com/enjoy-digital/versa_ecp5/blob/master/versa_ecp5.py#L20514:09
tpbTitle: versa_ecp5/versa_ecp5.py at master · enjoy-digital/versa_ecp5 · GitHub (at github.com)14:09
_florent_acathla: SoCCore is fine for you14:09
acathla_florent_, it works now, but I have 2 sram regions, it seems there is one by default (litex/soc/integration/soc_core.py).14:19
_florent_acathla: yes you can use another name14:20
acathlaIf I replace the sram_size by my Memory it does not work14:20
_florent_acathla: and use 0x30000000 as the firmware_ram in the example14:20
_florent_acathla: what's the error message?14:20
acathlamany lines ending with "raise IndexError"14:21
acathlawishbone.py", line 655, in <listcomp> , for i in range(bus_data_width//8)]14:22
acathla_florent_, and my initialization is something like Memory(width, depth, init=data)14:23
_florent_acathla: can you share your actual code?14:24
acathlaMy horrible code? hum14:24
acathla_florent_, I can also forget about my own Memory modules and use those sram with initialization14:29
_florent_ah yes, you can also do that14:32
acathla_florent_, do you have an example of how to read and write to sram through uart-bridge?15:32
acathlaI tried some "wb.write(wb.mems.s_ram,42)" but I have a AttributeError: 'CSRMemoryRegion' object has no attribute 'to_bytes'15:34
_florent_wb.write(addr, value), wb.read(addr) :)15:34
_florent_can you try wb.write(wb.mems.s_ram.base, 42)?15:34
acathlaah, right, I removed too much, it works !15:40
acathla_florent_, but if I use a SRAM Module, the only way to access it is through the wishbone bus...16:20
_florent_acathla: that's why you can choose if SRAM provide the memory or if you provide it16:21
_florent_acathla: you should be able to pass the Memory you create outside to SRAM16:24
acathlaI should...16:24
acathlaI can also use big CSR16:25
_florent_if you create a minimal design with the error, i'll look at that16:26
tpbTitle: ZeroBin (at sebsauvage.net)16:51
acathla_florent_, this code in targets/tinyfpga_bx/ will produce the same error as before16:51
acathlait just needs the standard base.py I think, may be I added some uart16:52
_florent_the issue is that the width of your memory is 8 bits and SRAM expect 32 bits17:05
acathlaOh that's all, ok =)17:11
acathlaThank you17:12
keesjacathla: I don't have the from targets.utils import csr_map_update19:52
keesjI have litex/soc/integration/soc_core.py:def csr_map_update19:53
keesjxobs: building the lm gnu toolchain was suprizingly easy(on ubuntu) e.g. following https://github.com/enjoy-digital/litex/blob/master/README#L9019:56
tpbTitle: litex/README at master · enjoy-digital/litex · GitHub (at github.com)19:56
keesjthere was no libc / syslib messing arround (so far)19:57
keesjI mean starting at line 108, not the conda method line 9019:58
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