Sunday, 2019-02-24

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somloI tried to synthesize the litedram nexys4ddr example (using the generated litedram_core.tcl script, and the placer fails with "IO placement failed due to overutilization. This design contains 780 i/o ports while the target  device: 7a100t package: csg324, contains only 210 available user I/O."13:14
somlothis is vivado 2018.2, btw13:14
daveshahsomlo: sounds like your top level module is wrong13:15
somloI'm guessing maybe the axi ("user ports" in") is the problem?13:16
somloas in, I don't need them when synthesizing a self contained SoC with vexriscv embedded cpu?13:17
somloI'm still confused about the architecture of litedram -- examples/ appears to spit out a ready-for-synthesis build/gateware/ directory, with a .tcl file, etc.13:26
somloit seems to include a CPU complete with bare-metal "firmware" that's supposed to speak "uart"13:27
somlonot clear how i'd get something I could connect to my own CPU/SoC, running my own bare-metal software13:28
somlodaveshah: when you built litedram for the ECP5 ( - what did your core_config struct look like?14:38
daveshahsomlo: have a look at
tpbTitle: GitHub - enjoy-digital/versa_ecp5: Versa ECP5 SoC based on LiteX (at
somlodoes this: mean you ended up using Diamond to build it?14:51
tpbTitle: versa_ecp5/ at master · enjoy-digital/versa_ecp5 · GitHub (at
daveshahThis branch uses nextpnr:
tpbTitle: GitHub - daveshah1/versa_ecp5_dram at trellis2 (at
daveshahbut stuff isn't upstream yet so I wouldn't recommend it14:52
somloI don't have Diamond, so if I do end up trying something on ecp5 it'll have to be the trellis version :)14:53
daveshahYou'll need and and
tpbTitle: GitHub - YosysHQ/nextpnr at placer_heap_ddrn (at
somloThanks! I'll tinker with this for the next couple of days (mixed in with some dayjob related travel), and maybe it will all start making sense by the time I get back, so the questions will hopefully get correspondingly less silly :) Thanks (again) for all the help, btw!15:04
_florent_somlo: in the standalone example, a cpu is embedded to do the initialization18:26
_florent_somlo: the uart pins are exposed, but that's mostly for debug to ease debug is the calibration fails18:26
_florent_somlo: you can leave it unconnected if you want, there are status pin that tells you when the calibration is done and the status18:27
_florent_the default example is configure for 2 ports, you can reduce it to one if you only want one18:28
_florent_but, you still need to connect the axi pins in your top since these pins are not I/Os18:29
_florent_if you want to test a self contained SoC for the Nexys4DDR, there is a target:
tpbTitle: litex/ at master · enjoy-digital/litex · GitHub (at

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