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| Kjetil | publicsdi? :P | 10:04 |
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| mithro | felix_: gah, guess we should have check the name before hand | 23:19 |
| mithro | felix_: I'll put together some alternative names | 23:20 |
| felix_ | ok, thx | 23:22 |
| felix_ | btw: the idea to put the chip with 1 lvds clock lane and 5 lvds data lanes that outputs 3g sdi on the single axiom extension board likely won't work, since the clock isn't really source synchronous; we would need another lvds pair to do that properly :/ | 23:28 |
| mithro | Hrm? | 23:32 |
| mithro | You mean we need to receive the clock and then generate a source synchronised version? | 23:33 |
| mithro | Is this with the Artix-7 on the expansion board? | 23:35 |
| felix_ | that was the idea without the artix7 on the sdi board | 23:36 |
| felix_ | LMH0340 | 23:36 |
| mithro | Okay, I haven't caught up with how the non-artix7 design would work? I'm assuming the IC is just a SERDES type thing? | 23:37 |
| felix_ | but we can't just put a clock chip on the board and route the clock to both fpga and sdi serializer from it; the clocks will have a big skew | 23:37 |
| felix_ | when i did the research for the sdi chips list i found that chip and thought that it would be a good candidate for a cheap 3g sdi interface for the axiom that only needs one high speed expansion slot | 23:38 |
| mithro | That IC is ~$20 USD in 1k quantities! | 23:38 |
| felix_ | stil cheaper than putting an artix7 and a maybe 4 euro sdi driver on a board | 23:39 |
| mithro | IIRC can get an Artix-7 15T -1 speed grade with GTP for about ~$15 USD in 1k quantities | 23:41 |
| mithro | I'm on my phone, so can't really check at the moment | 23:41 |
| felix_ | ok. iirc that chip is more expensive if you don't order it in a big quantity | 23:42 |
| mithro | The Atrix price drops pretty fast if you order large quantities | 23:42 |
| mithro | Specially if you are happy with the -1 speed grade part | 23:42 |
| felix_ | i'd really use the CSG325 and not the CPG236 package, since the smaller package will require a more expensive pcb | 23:43 |
| felix_ | well, the -1 only support 3g sdi | 23:43 |
| mithro | Digi-Key is about * 2 the price | 23:43 |
| mithro | That lm part seems to only be 3g too? | 23:44 |
| felix_ | yes | 23:44 |
| mithro | felix_: I'd have to look at it, but normally PCB cost is not a huge factor once you go past 10 units | 23:45 |
| mithro | (unless you need things like blind vias) | 23:46 |
| mithro | Although I know the apertus project has some requirements around ethical sourcing | 23:47 |
| mithro | Btw Where did we settle with Dev boards? | 23:47 |
| felix_ | 0,5mm pitch might require via in pad | 23:48 |
| felix_ | iirc we haven't really discussed the devboard thing | 23:48 |
| mithro | Yeah, that does get more expensive and also makes construction more expensive | 23:48 |
| mithro | S/construction/assembly/ | 23:49 |
| felix_ | but since we want to have support for at least one easily available fpga devboard, i would really like to develop the sdi support on a fpga devboard with a sdi fmc module and the port it to the custom board | 23:50 |
| mithro | felix_: Xilinx have a good white paper on "ddr3 low cost PCB for Artix 7" | 23:50 |
| felix_ | on the custom board: as a first step we planned to make a base board for the small trenz artix7 module with the sdi driver/equalizer chip to test that part of the design and then do a pcb with that and an artix7 and with a dual axiom connector | 23:51 |
| mithro | felix_: no argument from me about using an existing known working dev board before doing custom hardware | 23:51 |
| felix_ | and porting the design to be able to use a sdi sfp will probably also be quite easy, but not as a first step | 23:52 |
| mithro | Yeah | 23:52 |
| mithro | felix_: are these plans documented anywhere apart from IRC logs on this / apertus channel? | 23:53 |
| felix_ | yeah, when i was in vienna and talked with herbert and sebastian, we talked about how to develop the sdi core without having to have to buy a big devboard, but since you want support for a big devboard anyway, that's not really a point any more | 23:54 |
| felix_ | sadly not; haven't gotten around to document that :/ | 23:54 |
| felix_ | but those plans are still not 100% finished; i'll try to write down a bit more stuff in the next days | 23:55 |
| mithro | Would be good to have a doc with things just to make sure everyone has similar understanding - happy if it's extremely rough and it's bound to change | 23:56 |
| felix_ | yep, before buying any stuff, we really should have a list and at least a rough plan | 23:57 |
| felix_ | i'll need the first two weeks to read and understand the sdi spec and learn/get used to migen/litex | 23:58 |
| felix_ | maybe a bit less, but as a rough plan | 23:59 |
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