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| F4PGASlackBridge | <umartinezcorral> @timo.callahan see https://f4pga.readthedocs.io/en/latest/development/changes.html. We added a section to the main documentation of F4PGA, to keep track of known to work combinations of f4pga-arch-defs, f4pga-examples and f4pga. I guess the last working setup for you is `1` (https://f4pga.readthedocs.io/en/latest/development/changes.html#id4). Changing to `2` | 11:36 |
|---|---|---|
| F4PGASlackBridge | (https://f4pga.readthedocs.io/en/latest/development/changes.html#id3) should be easy. You will get more recent arch-defs, and that is the first revision of f4pga-examples where f4pga is pinned. Then, I recommend skipping `3` and updating to `4` (https://f4pga.readthedocs.io/en/latest/development/changes.html#id1). | 11:36 |
| tpb | Title: Changes — F4PGA documentation (at f4pga.readthedocs.io) | 11:36 |
| tpb | Title: Changes — F4PGA documentation (at f4pga.readthedocs.io) | 11:36 |
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| Curious | Hello. Does perhaps anyone have the knowledge and spar time to answer some questions about the prjxray database? | 12:43 |
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| hansfbaier | Curious: Yes, I can answer some questions. | 12:53 |
| hansfbaier | Curious: Better just ask, don't ask to ask | 12:54 |
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| Curious | Alright. I'm working on some university project and need to understand the effect of specific fasm features/bits of CLBs and INTs. Some are self-explanatory (e.g. CLBLL_L.SLICEL_X1.DLUT.INIT[00]) but others are not as evident (e.g. INT_R.ER1BEG3.EL1END2). Is there a way i can look up their functions? Or is there a Xilinx document that explains | 13:01 |
| Curious | features like INT_R.ER1BEG3.EL1END2? | 13:01 |
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| hansfbaier | Curious: I didn't yet spend much time on CLBs and INTs, but you can look those up in the device view in Vivado (which you get after you open the implementation) | 20:07 |
| hansfbaier | \quit | 20:07 |
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| Curious | okay thanks for the tip | 20:22 |
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| F4PGASlackBridge | <timo.callahan> @umartinezcorral thanks I hadn't noticed that page! I did see your update to F4PGA_TIMESTAMP and _HASH in F4PGA examples and used it to fix the situation in CFU Playground. Does one of the hashes correspond to which one to use to pin `prjxray` and `f4pga-xc-fasm` in my `requirements-symbiflow.txt`? Or should those not be pinned? | 21:24 |
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| F4PGASlackBridge | <umartinezcorral> @timo.callahan that page did not exist until yesterday :) I did it during the weekend. The timestamp and hashes correspond to repository f4pga-arch-defs. It's the CI run time and commit used to generate the tarballs. Those are unrelated to the dependencies. The versions of prjxray and f4pga-xc-fasm are defined in the environment.yml of the Conda env you use. I guess it's | 21:52 |
| F4PGASlackBridge | https://github.com/tcal-x/CFU-Playground/blob/3dee6993792e3b81408d002439a5a900eb37580d/conf/requirements-symbiflow.txt#L24-L25 in CFU. | 21:52 |
| F4PGASlackBridge | <umartinezcorral> Actually, you can pin f4pga in the requirements-symbiflow.txt file. Since you are using arch-defs 20220729 (https://github.com/google/CFU-Playground/pull/636/files) I recommend pinning to https://github.com/chipsalliance/f4pga/commit/8c411eb74e4bb23d1ec243a1515b9bfb48e2cd83 | 21:54 |
| F4PGASlackBridge | <timo.callahan> Do you mean for the line with `main.zip`? | 21:56 |
| F4PGASlackBridge | <umartinezcorral> Yes `s/main/HASH/`. E.g. https://github.com/chipsalliance/f4pga-examples/blob/main/common/requirements.txt#L18 | 21:56 |
| F4PGASlackBridge | <umartinezcorral> GitHub provides zipfiles for any ref (either branch name, tag or commit hash). | 21:57 |
| F4PGASlackBridge | <timo.callahan> OK thanks! | 21:59 |
| mithro | https://github.com/byuccl/bfat | 22:08 |
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