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| F4PGASlackBridge | <acomodi> @mahnoor I have read through the draft and I think it is headed towards the right direction, I'll add some further comments on the doc, but I believe you may proceed and upload the draft directly on GSoC | 08:14 |
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| F4PGASlackBridge | <tmichalak> Hi @gmakkena, I saw you finished the PR in f4pga-database-visualizer. Great. We will open more smaller issues so that you can take a look and maybe start working on those. In the meantime, since the deadline for submitting project proposals is April 19th, maybe you could prepare a draft of your proposal and submit it via the GSoC webpage? You will be able to change it afterwards, but it's required to submit | 08:16 |
| F4PGASlackBridge | something to have a chance of being accepted. | 08:16 |
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| F4PGASlackBridge | <gmakkena> Hi Tomasz. I will submit the proposal for this in the GSOC page before deadline. If I have any questions, I shall ping in the channel. Thank you for the opportunity to work in the PR. | 08:58 |
| F4PGASlackBridge | <tmichalak> Sure, ping on the channel or on GH | 08:58 |
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| F4PGASlackBridge | <gmakkena> I work at a University and I am encouraging few of my best students to submit proposals on GSOC (chips alliance). We are planning to work on Project 2 (DSP hard block integration in F4PGA). Do you have any tasks regarding that project so that I shall ask my students to start on it? I have exposure to Verilog HDL as well. | 09:03 |
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| F4PGASlackBridge | <tmichalak> Oh, that is great to hear. Let me check with @mkurc who is author of this idea | 10:37 |
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| F4PGASlackBridge | <me1> @hansfbaier You click the little red x / green tick in the bar above the directory listing | 22:30 |
| F4PGASlackBridge | <me1> It says something like "3,570 commits" | 22:31 |
| F4PGASlackBridge | <me1> The ticks are easier to see if you go to this page -> https://github.com/f4pga/prjxray/commits/master | 22:31 |
| F4PGASlackBridge | <talhaahmedashraf> Hello, I'm writing to share my interest about F4PGA toolchain integration in mainline Edalize. This project is mentioned on the GSoC ideas 2022 webpage. Actually, I was looking for a suitable organization and project to apply for this summer. I am a little late in finding this project, but I will surely meet the proposal submission due of April 19th. I'm excited to learn more about the idea and discuss it | 23:51 |
| F4PGASlackBridge | with you. Currently I am studying Software Engineering also working as a Research Intern in Micro-Electronics Research Lab. Currently, I am working on: 1) RISCV based SoC Generator which leads to the generation of bitstream by using (Symbiflow) F4PGA. 2) Designing real-world Tensor Flow Lite models and running on to the RISCV based processors. LinkedIn Github | 23:51 |
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