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| lkcl | marzoul: fyi the same bug in symbiflow related to CARRY4, which i discussed with acomodi when this was the #symbiflow channel, is also present in nextpnr-xilinx | 11:15 |
|---|---|---|
| lkcl | gatecat ^ | 11:15 |
| lkcl | it does not show up when using RISC-V 32-bit cores because those never create carry-chains of more than 23-25 CARRY4 blocks | 11:16 |
| lkcl | only if you attempt a 64-bit core using e.g. a divide unit with 128-bit remainder/quotients e.g. in Power ISA 64-bit do you run smack into this problem | 11:17 |
| lkcl | toshywoshy, as discussed yesterday ^ | 11:17 |
| lkcl | the symptoms for symbiflow are that it bombs out with an error | 11:18 |
| lkcl | the symptoms for nextpnr-xilinx are that it completely locks up and fails to complete, going into an infinite loop | 11:18 |
| lkcl | as long as you stay below about 4x23-or-so (95) bit add, subtract or compare, you're "fine" | 11:19 |
| lkcl | the "workaround" is to use "-nocarry" to yosys "synth_xilinx" | 11:20 |
| lkcl | -nocarry | 11:20 |
| lkcl | do not use XORCY/MUXCY/CARRY4 cells in output netlist | 11:20 |
| lkcl | the proper solution is to fix the synth_xilinx techmap so that it splits anything above 95-or-thereabouts bits into separate adds/subs/cmps with an explicit carry-signal | 11:21 |
| lkcl | x[128], y[128] | 11:22 |
| lkcl | add(x, y) | 11:22 |
| lkcl | --> | 11:22 |
| lkcl | z[0:97] = add(x[0:96], y[0:96]) | 11:23 |
| lkcl | z[96:128] = add(z[96], x[96:128], y[96:128]) | 11:24 |
| lkcl | you get the general idea i'm sure | 11:24 |
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| * dmorn Rolls a 6 sided dice and gets 1 | 15:01 | |
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| mithro | @acomodi - Can you help with https://github.com/verilog-to-routing/vtr-verilog-to-routing/issues/1994 ? | 17:08 |
| F4PGASlackBridge | <acomodi> mithro: Sure thing, I'll reply shortly | 17:09 |
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| hansfbaier | Which distribution version is recommended for developing prjxray? I currently use Ubuntu 20.04.3 LTS but the cmake version that comes with it seems to be too old with latest prjxray | 22:45 |
| hansfbaier | ? | 22:45 |
| hansfbaier | Ah it used the old version from the Vivado settings file. That was the problem. | 23:17 |
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| tcal | This is a Colab I made of a yosys/nextpnr-nexus build for a LiteX/Vex/accelerator on a Crosslink Nexus chip (lifcl-17). This shows off the Nexus support added by Gatecat, and various improvements added by Antmicro. Scroll down to see a plot of the final placement and critical path. Note the yosys script invokes the new dsp-ff mapping optimization plugin by Antmicro. | 23:45 |
| tcal | https://colab.research.google.com/drive/1rl9gu-_uRK8MLA3z07HMgP2L1dZOw1jd#scrollTo=DQpjM1dKO03w | 23:45 |
| tpb | Title: Google Colab (at colab.research.google.com) | 23:45 |
| tcal | Use this link to start at the top: https://colab.research.google.com/drive/1rl9gu-_uRK8MLA3z07HMgP2L1dZOw1jd | 23:46 |
| tpb | Title: Google Colab (at colab.research.google.com) | 23:46 |
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